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This integration bridges the gap between high-level logical compilation and realistic physical error modeling, allowing hardware teams to simulate fault-tolerant protocols like lattice surgery under actual device noise conditions. By combining CUDA-Q Logical's workload definitions with Plaquette's physics-based noise models, developers can now accurately assess how factors such as qubit leakage impact circuit-noise thresholds without relying on idealized assumptions. This workflow advancement is critical for validating error correction architectures before deployment on real quantum hardware.

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QC Design Integrates Plaquette With NVIDIA CUDA-Q Logical for Hardware-Realistic QEC Simulation

The Quantum InsiderSeptember 15, 20263 min read

Insider Brief PRESS RELEASE — QC Design today announced an integration between Plaquette, its design-automation platform for fault-tolerant quantum computing (FTQC), and NVIDIA CUDA-Q Logical, the open, extensible logical layer of the CUDA-Q platform. This collaboration enables quantum hardware teams to perform accurate simulations of lattice surgery and other logical protocols using realistic, physics-based hardware […]

QC Design has integrated its Plaquette design-automation platform with NVIDIA CUDA-Q Logical to enable hardware-realistic simulations of lattice surgery and other fault-tolerant quantum protocols. The integration combines CUDA-Q Logical’s logical workload and QEC architecture layer with Plaquette’s device-specific noise models to assess logical protocols under physical hardware errors. In an initial simulation, QC Design found…

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