analiza aiqbench

This integration bridges the gap between high-level logical compilation and realistic physical error modeling, allowing hardware teams to simulate fault-tolerant protocols like lattice surgery under actual device noise conditions. By combining CUDA-Q Logical's workload definitions with Plaquette's physics-based noise models, developers can now accurately assess how factors such as qubit leakage impact circuit-noise thresholds without relying on idealized assumptions. This workflow advancement is critical for validating error correction architectures before deployment on real quantum hardware.