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This integration bridges high-level quantum error correction compilation with device-specific physical noise models, enabling more accurate fault-tolerant simulations that account for continuous non-Pauli errors like leakage. By quantifying how specific hardware imperfections degrade theoretical noise thresholds, the collaboration provides a critical data-backed baseline for validating realistic FTQC deployment roadmaps.

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QC Design Integrates Plaquette Platform with NVIDIA CUDA-Q Logical for Hardware-Realistic FTQC Simulation

Quantum Computing ReportSeptember 15, 20262 min read

QC Design has integrated its Plaquette platform with NVIDIA CUDA-Q Logical, announced on September 14, 2026. This integration allows for hardware-realistic fault-tolerant quantum computing (FTQC) simulations by connecting high-level quantum error correction (QEC) circuit compilation with device-specific physical noise models. This enables evaluation of QEC code structures under continuous non-Pauli noise models, addressing discrepancies in traditional FTQC resource estimation. An initial study showed a 0.2% leakage rate on two-qubit entangling gates degraded the fault-tolerant circuit noise threshold by approximately 60%. The post QC Design Integrates Plaquette Platform with NVIDIA CUDA-Q Logical for Hardware-Realistic FTQC Simulation appeared first on Quantum Computing Report.

Fault-tolerant quantum design automation developer QC Design has announced an integration between its flagship platform, Plaquette, and NVIDIA CUDA-Q Logical. Announced on September 14, 2026,…

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