aiqbench takeChips & Infra

Taiyo Holdings' development of a three-layer RDL with 700-nm precision represents a critical advancement in interconnect technology required for advanced semiconductor packaging. This breakthrough enables finer-pitch wiring essential for next-generation chips, validating the dual damascene process as a necessity for sub-1.6-micrometer pitches. The collaboration with imec confirms that these materials offer the high resolution and electrical performance needed to sustain Moore's Law scaling.

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Taiyo Holdings builds three-layer RDL with 700-nm precision

Quantum ZeitgeistSeptember 10, 20262 min read

Taiyo Holdings launches the next generation semiconductor packaging material, FPIM Series, achieving its first three-layer RDL formation with 700-nm CD on 12-inch wafers. The company presented this development, co-authored with imec, at the IEEE ESTC 2026 conference on September 10, 2026.

Taiyo Holdings achieved a 700-nanometer critical dimension in its first three-layer redistribution layer formation on 12-inch wafers, a key step toward finer-pitch wiring for advanced semiconductor packaging, the company says. The company presented these findings on its FPIM Series material at the IEEE ESTC…

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