aiqbench analysis
This research addresses a critical gap in formal verification by enabling rapid, computationally efficient correction of control systems when they violate Signal Temporal Logic (STL) specifications under uncertainty. By leveraging logical dependency tracking and three-valued semantics, the method extracts compact constraint sets in milliseconds, allowing for certified probabilistic bounds without resorting to combinatorial enumeration. The approach demonstrates that formally guaranteed safety corrections are feasible even for nonlinear systems with nested temporal logic requirements, advancing the practical deployment of robust AI-driven control algorithms.
Fast Constraint Extraction for Corrective Control under STL Specifications via Logical Dependency Tracking
arXiv:2609.09439v1 Announce Type: cross Abstract: Ensuring the satisfaction of Signal Temporal Logic (STL) specifications under uncertainty is challenging, as reachability-based monitoring provides guarantees but does not indicate how to restore satisfaction when it becomes indeterminate. A key difficulty is identifying which uncertain components actually affect global satisfaction, especially for nested formulas. This paper introduces a logical dependency tracking framework that propagates uncertainty through the STL structure and captures the causal contribution of reachable sets to satisfaction. By associating markers to uncertain predicates and propagating them via three-valued semantics, we extract in milliseconds a compact Disjunctive Normal Form (DNF) of sufficient constraints, avoiding combinatorial enumeration. As an application, we formulate control correction as a minimum-effort optimization problem. Using zonotopic reachability, the derived constraints are enforced via linear programming, yielding corrections that guarantee STL satisfaction under bounded uncertainty and provide certified probabilistic bounds in the stochastic case. We demonstrate the approach on a nonlinear system with nested STL specifications, showing that dependency tracking enables efficient and formally guaranteed correction. The tracking implementation is available at https://github.com/Antoine-Bst/STL-Three-Valued-Clause-Filtering/.
Abstract:Ensuring the satisfaction of Signal Temporal Logic (STL) specifications under uncertainty is challenging, as reachability-based monitoring provides guarantees but does not indicate how to restore satisfaction when it becomes indeterminate. A key difficulty is identifying which uncertain components actually affect global satisfaction, especially for nested formulas. This paper introduces a logical dependency tracking framework that propagates uncertainty through the STL structure and captures the causal contribution of reachable sets to satisfaction. By associating markers to uncertain predicates and propagating them via three-valued semantics, we extract in milliseconds a compact Disjunctive Normal Form (DNF) of sufficient constraints, avoiding combinatorial enumeration. As an application, we formulate control correction as a minimum-effort optimization problem. Using zonotopic reachability, the derived constraints are enforced via linear programming, yielding corrections that guarantee STL satisfaction under bounded uncertainty and provide certified probabilistic bounds in the stochastic case. We demonstrate the approach on a nonlinear system with nested STL specifications, showing that dependency tracking enables efficient and formally guaranteed correction. The tracking implementation is available at this https URL.
Logic in Computer Science (cs.LO); Robotics (cs.RO); Systems and Control (eess.SY)
arXiv:2609.09439 [cs.LO]
(or arXiv:2609.09439v1 [cs.LO] for this version)
https://doi.org/10.48550/arXiv.2609.09439 Focus to learn more arXiv-issued DOI via DataCite (pending registration)
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