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SignatureIP Unveils MesoLink, a Mesochronous Bridge for PCIe/CXL Validation
A PCIe/CXL device under test keeps its native generation, lane width and timing; the FPGA side runs full-rate SerDes. Plug-and-play prototyping and emulation. SANTA CLARA, Calif., Sept. 16, 2026 — SignatureIP, a pioneer and next-generation scalable Silicon Infrastructure Solutions provider, has announced MesoLink, its new Mesochronous Connectivity Bridge IP core that sits between a PCIe/CXL […] The post SignatureIP Unveils MesoLink, a Mesochronous Bridge for PCIe/CXL Validation appeared first on HPCwire.
A PCIe/CXL device under test keeps its native generation, lane width and timing; the FPGA side runs full-rate SerDes. Plug-and-play prototyping and emulation. SANTA CLARA, Calif., Sept. 16, 2026 — SignatureIP, a pioneer and next-generation scalable Silicon Infrastructure Solutions provider, has announced MesoLink, its new Mesochronous Connectivity Bridge IP core that sits between a PCIe/CXL Device Under Test (DUT) and the FPGA SerDes in system-level verification, emulation and prototyping…
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