Can Agents Design Better Chips with a Higher Level Abstraction?

Title:Can Agents Design Better Chips with a Higher Level Abstraction?

Abstract:Large Language Model (LLM) agents are increasingly being explored for chip design, but most existing approaches operate directly at RTL. We ask whether agents can design better chips by leveraging higher-level abstractions. We compare Direct RTL Design, Agent-based HLS Design, Post-Compiler HLS Refinement, and Post-HLS RTL Refinement, and combine Agent-based HLS Design with Post-HLS RTL Refinement as Agent-based HLS with RTL Refinement (AHRR). We use FPGAs as a practical, easy-to-deploy platform for end-to-end evaluation, but note that the design-flow tradeoffs we study are largely independent of the target technology. Across a diverse 11-tasks benchmark suite, AHRR achieves a 2.6$\times$ geometric-mean speedup over Direct RTL Design across our benchmark suite. Case studies show that HLS distills design knowledge into abstractions that agents can leverage, while RTL refinement recovers lower-level optimization opportunities. Together, these results make AHRR a promising workflow for agentic chip design. The code and evaluation artifacts are available at this https URL.

Artificial Intelligence (cs.AI); Hardware Architecture (cs.AR)

arXiv:2609.21157 [cs.AI]

(or arXiv:2609.21157v1 [cs.AI] for this version)

https://doi.org/10.48550/arXiv.2609.21157 Focus to learn more arXiv-issued DOI via DataCite (pending registration)

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