aiqbench analysis
SECDA-DSE integrates Large Language Models into the FPGA design flow to automate hardware-software co-design, successfully generating synthesizable accelerators for diverse AI kernels like convolution and matrix transpose. By leveraging reasoning-guided exploration and a feedback loop, the framework reduces reliance on manual domain expertise while effectively capturing kernel-specific trade-offs between compute parallelism and data movement. This approach demonstrates a viable path toward autonomous accelerator generation, significantly streamlining the exploration of complex hardware design spaces for modern AI workloads.
Towards Autonomous Accelerator Design: FPGA Accelerator Generation with SECDA
arXiv:2606.11117v1 Announce Type: cross Abstract: Designing FPGA-based accelerators for modern artificial intelligence workloads requires exploring a large and complex hardware design space that involves architectural parameters, data flow strategies, and memory hierarchies, making the process very time consuming. While existing methodologies such as SECDA enable rapid hardware-software co-design through SystemC simulation and FPGA execution, identifying efficient accelerator configurations remains a largely manual process requiring extensive domain knowledge. SECDA-DSE is a framework that integrates Large Language Models (LLMs) into the SECDA ecosystem to guide design space exploration (DSE) of FPGA-based accelerators. It combines a structured DSE Explorer for generating candidate architectures with an LLM Stack that performs reasoning-guided exploration using retrieval-augmented generation and chain-of-thought prompting, coupled with a feedback loop for iterative and reinforced refinement. Building on our previous work introducing SECDA-DSE, this paper extends its evaluation by generating three accelerator designs, including element-wise vector multiplication, 2D convolution, and matrix transpose, and performing end-to-end execution on FPGA hardware. The results show that SECDA-DSE can generate SECDA-compliant accelerator designs that are successfully synthesized and executed on FPGA hardware. Furthermore, the generated designs capture kernel-specific trade-offs between compute parallelism and data movement, highlighting the potential of LLM-guided exploration to adapt architectural configurations across diverse workloads while reducing exploration time and the need for extensive human expertise.
Abstract:Designing FPGA-based accelerators for modern artificial intelligence workloads requires exploring a large and complex hardware design space that involves architectural parameters, data flow strategies, and memory hierarchies, making the process very time consuming. While existing methodologies such as SECDA enable rapid hardware-software co-design through SystemC simulation and FPGA execution, identifying efficient accelerator configurations remains a largely manual process requiring extensive domain knowledge. SECDA-DSE is a framework that integrates Large Language Models (LLMs) into the SECDA ecosystem to guide design space exploration (DSE) of FPGA-based accelerators. It combines a structured DSE Explorer for generating candidate architectures with an LLM Stack that performs reasoning-guided exploration using retrieval-augmented generation and chain-of-thought prompting, coupled with a feedback loop for iterative and reinforced refinement. Building on our previous work introducing SECDA-DSE, this paper extends its evaluation by generating three accelerator designs, including element-wise vector multiplication, 2D convolution, and matrix transpose, and performing end-to-end execution on FPGA hardware. The results show that SECDA-DSE can generate SECDA-compliant accelerator designs that are successfully synthesized and executed on FPGA hardware. Furthermore, the generated designs capture kernel-specific trade-offs between compute parallelism and data movement, highlighting the potential of LLM-guided exploration to adapt architectural configurations across diverse workloads while reducing exploration time and the need for extensive human expertise.
Hardware Architecture (cs.AR); Artificial Intelligence (cs.AI); Performance (cs.PF)
arXiv:2606.11117 [cs.AR]
(or arXiv:2606.11117v1 [cs.AR] for this version)
https://doi.org/10.48550/arXiv.2606.11117 Focus to learn more arXiv-issued DOI via DataCite (pending registration)
arXivLabs is a framework that allows collaborators to develop and share new arXiv features directly on our website.
Both individuals and organizations that work with arXivLabs have embraced and accepted our values of openness, community, excellence, and user data privacy. arXiv is committed to these values and only works with partners that adhere to them.
Have an idea for a project that will add value for arXiv's community? Learn more about arXivLabs.
Full text under the publisher's open licence · 307 words
Related coverage

Processor Delivers 100× Computing Boost for Deep Space Missions
Quantum Zeitgeist · May 22, 2026

Quantum Cyber names Tzvi Lev to lead Middle East sales push
Quantum Zeitgeist · Sep 28, 2026

CypherGenics’ FASTKAT secures data for a post-quantum world
Quantum Zeitgeist · Aug 26, 2026

Synopsys Advances Agentic AI Chip Design with AMD and Microsoft
eejournal.com · Jul 28, 2026