aiqbench analysis
This research demonstrates that implementing spike-aware INT8 execution strategies on commodity CPUs can significantly improve the efficiency of spiking language models, achieving up to 47.9 tokens/s while reducing memory footprint by over 60%. The study validates that specific activation layouts and quantized kernels are essential for viable CPU deployment of these architectures, offering a practical path toward energy-efficient inference without relying on specialized hardware.
Spike-Aware INT8 Execution for Spiking Language Models on Commodity CPUs
arXiv:2606.03026v2 Announce Type: replace-cross Abstract: Binary spike activations allow a language-model runtime to read only active weight columns and replace multiplications by weight sums. We implement this execution strategy in C++ for an 874M-parameter spike-gated language model. Sparse projections use column-major INT8 weights, integer accumulation, and one scale application per output channel; dense projections retain row-major access and FP32 activations. In a single-thread comparison using an early checkpoint, INT8 achieves 23.31 tokens/s versus 9.82 for FP32, while reducing weight storage from 3355.2 to 1087.4 MiB. A variant using INT4 on dense projections saves a further 17.4% of storage but reduces decode throughput by 46.6%. On an AMD Ryzen 7 5800X, the final INT8 checkpoint achieves 22.63 tokens/s on one thread and 47.90 on four threads; 512-token prefill reaches 94.68 tokens/s on eight threads. A separate ARM output-head case study records higher trimmed decode-window energy metrics for two candidate-verification configurations. The results characterize how activation-specific layouts and quantized kernels support CPU deployment of a spike-gated language model.
Abstract:Binary spike activations allow a language-model runtime to read only active weight columns and replace multiplications by weight sums. We implement this execution strategy in C++ for an 874M-parameter spike-gated language model. Sparse projections use column-major INT8 weights, integer accumulation, and one scale application per output channel; dense projections retain row-major access and FP32 activations. In a single-thread comparison using an early checkpoint, INT8 achieves 23.31 tokens/s versus 9.82 for FP32, while reducing weight storage from 3355.2 to 1087.4 MiB. A variant using INT4 on dense projections saves a further 17.4% of storage but reduces decode throughput by 46.6%. On an AMD Ryzen 7 5800X, the final INT8 checkpoint achieves 22.63 tokens/s on one thread and 47.90 on four threads; 512-token prefill reaches 94.68 tokens/s on eight threads. A separate ARM output-head case study records higher trimmed decode-window energy metrics for two candidate-verification configurations. The results characterize how activation-specific layouts and quantized kernels support CPU deployment of a spike-gated language model.
13 pages, 3 figures, 11 tables. Revised presentation and evaluation; added numerical validation and an ARM wall-power case study; withdrawn invalid pure-INT4 results and clarified comparison protocols
Neural and Evolutionary Computing (cs.NE); Artificial Intelligence (cs.AI); Machine Learning (cs.LG)
arXiv:2606.03026 [cs.NE]
(or arXiv:2606.03026v2 [cs.NE] for this version)
Full text under the publisher's open licence · 207 words
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