aiqbench analysis
SparsePixels introduces an FPGA-specific architecture for sparse convolutional neural networks, significantly reducing inference latency by skipping computations over inactive pixels in data like neutrino interaction images. This approach achieves a 73x speedup with constant runtime performance independent of input density, offering a practical solution for high-speed scientific computing where standard dense CNNs are inefficient.
SparsePixels: Efficient Convolution for Sparse Data on FPGAs
arXiv:2512.06208v4 Announce Type: replace-cross Abstract: Inference of standard convolutional neural networks (CNNs) on FPGAs often incurs high latency and a long initiation interval due to the deep nested loops required to densely convolve every input pixel regardless of its feature value. However, input features can be spatially sparse in some image data, where semantic information may occupy only a small fraction of the pixels and most computation would be wasted on empty regions. In this work, we introduce SparsePixels, a framework that implements sparse convolution on FPGAs by selectively retaining and computing on a small subset of active input pixels while ignoring the rest, reducing the per-layer compute from $O(HWK^2C_{\text{in}}C_{\text{out}})$ to $O(n^2C_{\text{in}}C_{\text{out}})$ and the storage from $O(HWC)$ to $O(nC)$ when $n^2\ll HW$. Because computation always runs over a single pre-specified pixel budget that is frozen at synthesis, the inference latency is data-independent and constant at runtime. We show that, for identifying neutrino interactions in naturally sparse LArTPC images with 4k pixels, a standard CNN with a compact size of 4k parameters incurs an inference latency of 48.665 $\mu$s on an FPGA, whereas a sparse CNN of the same base architecture, computing on less than 1% of the input pixels, achieves a $\times 73$ speedup to 0.665 $\mu$s with resource utilization well within on-chip budgets, trading only a small percent-level performance loss. This work aims to benefit future algorithm development for efficient data readout in modern experiments with strict latency requirements of microseconds or below.
Abstract:Inference of standard convolutional neural networks (CNNs) on FPGAs often incurs high latency and a long initiation interval due to the deep nested loops required to densely convolve every input pixel regardless of its feature value. However, input features can be spatially sparse in some image data, where semantic information may occupy only a small fraction of the pixels and most computation would be wasted on empty regions. In this work, we introduce SparsePixels, a framework that implements sparse convolution on FPGAs by selectively retaining and computing on a small subset of active input pixels while ignoring the rest, reducing the per-layer compute from $O(HWK^2C_{\text{in}}C_{\text{out}})$ to $O(n^2C_{\text{in}}C_{\text{out}})$ and the storage from $O(HWC)$ to $O(nC)$ when $n^2\ll HW$. Because computation always runs over a single pre-specified pixel budget that is frozen at synthesis, the inference latency is data-independent and constant at runtime. We show that, for identifying neutrino interactions in naturally sparse LArTPC images with 4k pixels, a standard CNN with a compact size of 4k parameters incurs an inference latency of 48.665 $\mu$s on an FPGA, whereas a sparse CNN of the same base architecture, computing on less than 1% of the input pixels, achieves a $\times 73$ speedup to 0.665 $\mu$s with resource utilization well within on-chip budgets, trading only a small percent-level performance loss. This work aims to benefit future algorithm development for efficient data readout in modern experiments with strict latency requirements of microseconds or below.
Hardware Architecture (cs.AR); Machine Learning (cs.LG); High Energy Physics - Experiment (hep-ex)
arXiv:2512.06208 [cs.AR]
(or arXiv:2512.06208v4 [cs.AR] for this version)
https://doi.org/10.48550/arXiv.2512.06208 Focus to learn more arXiv-issued DOI via DataCite
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