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This collaboration demonstrates a critical shift toward diversifying AI hardware beyond x86 and ARM by validating AMD's ROCm stack on RISC-V architectures. While currently a demonstration, the ability to run large models like Gemma4-E2B on SiFive CPUs with AMD GPUs signals potential future acceleration for hyperscalers seeking supply chain resilience. The success of this port will determine if RISC-V can become a viable primary compute substrate for next-generation datacenter AI workloads.

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SiFive and AMD Collaborate to Optimize AMD ROCm on RISC-V Datacenter Servers

HPCwireSeptember 15, 20262 min read

Open-source software and open-standard architectures to accelerate next-generation datacenter AI compute SANTA CLARA, Calif., Sept. 15, 2026 — Today at the AI Infra Summit, SiFive, Inc., and AMD showcased a demonstration of AMD ROCm running on SiFive’s recently announced BigSky Datacenter Development Platform. In a demonstration-only system, the companies showed the ability to run the modern […] The post SiFive and AMD Collaborate to Optimize AMD ROCm on RISC-V Datacenter Servers appeared first on HPCwire.

SANTA CLARA, Calif., Sept. 15, 2026 — Today at the AI Infra Summit, SiFive, Inc., and AMD showcased a demonstration of AMD ROCm running on SiFive’s recently announced BigSky Datacenter Development Platform. In a demonstration-only system, the companies showed the…

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