aiqbench analysis
RollPlace advances chip design automation by integrating Monte Carlo Tree Search with reinforcement learning to optimize macro placement in electronic design automation (EDA). This approach overcomes the limitations of single-shot generation methods, offering a scalable framework that efficiently refines layouts through a two-stage optimization strategy. The research demonstrates significant performance gains on standard benchmarks, marking a meaningful step forward in applying advanced AI techniques to complex hardware synthesis problems.
RollPlace: Improving Macro Placement via Monte Carlo Rollout Search
arXiv:2610.06316v1 Announce Type: new Abstract: The application of Reinforcement Learning (RL) in Electronic Design Automation (EDA), particularly for chip placement, has attracted considerable attention in recent years. While existing machine learning (ML)-based approaches have achieved notable progress, they predominantly focus on generating optimal layouts in a single attempt, often producing solutions that require subsequent refinement. To address this limitation, we propose RollPlace, a novel and generalized macro placement framework. RollPlace adopts a two-stage optimization strategy: generating initial placement solutions via machine learning methods or heuristic-based strategies, and refining these layouts efficiently by adjusting specific macros derived from the initial stage. This strategy circumvents the sequential generation constraints inherent in traditional RL-based placement methods. Furthermore, RollPlace seamlessly integrates Monte Carlo Tree Search (MCTS) to balance exploration and exploitation, and employs a rollout mechanism for efficient local search. Extensive experiments on the ISPD 2005 benchmark demonstrate that RollPlace outperforms state-of-the-art methods. Additionally, end-to-end experimental results based on OpenROAD across 19 benchmarks show that RollPlace excels in multiple metrics. The proposed framework offers a robust and scalable solution for addressing the growing complexity of modern chip design challenges.
Abstract:The application of Reinforcement Learning (RL) in Electronic Design Automation (EDA), particularly for chip placement, has attracted considerable attention in recent years. While existing machine learning (ML)-based approaches have achieved notable progress, they predominantly focus on generating optimal layouts in a single attempt, often producing solutions that require subsequent refinement. To address this limitation, we propose RollPlace, a novel and generalized macro placement framework. RollPlace adopts a two-stage optimization strategy: generating initial placement solutions via machine learning methods or heuristic-based strategies, and refining these layouts efficiently by adjusting specific macros derived from the initial stage. This strategy circumvents the sequential generation constraints inherent in traditional RL-based placement methods. Furthermore, RollPlace seamlessly integrates Monte Carlo Tree Search (MCTS) to balance exploration and exploitation, and employs a rollout mechanism for efficient local search. Extensive experiments on the ISPD 2005 benchmark demonstrate that RollPlace outperforms state-of-the-art methods. Additionally, end-to-end experimental results based on OpenROAD across 19 benchmarks show that RollPlace excels in multiple metrics. The proposed framework offers a robust and scalable solution for addressing the growing complexity of modern chip design challenges.
Artificial Intelligence (cs.AI)
arXiv:2610.06316 [cs.AI]
(or arXiv:2610.06316v1 [cs.AI] for this version)
https://doi.org/10.48550/arXiv.2610.06316 Focus to learn more arXiv-issued DOI via DataCite (pending registration)
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 45, no. 7, pp. 3155-3168, July 2026
https://doi.org/10.1109/TCAD.2025.3635566 Focus to learn more DOI(s) linking to related resources
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