RISC-V and machine learning: a survey

Abstract:The intersection of open-source processor architectures and machine learning is driving the demand for customizable, efficient, and accessible hardware. This survey examines the state of the RISC-V ISA in machine learning applications, analyzing current capabilities, challenges, and future directions based on recent research. The analysis covers academic and commercial implementations, software frameworks, and real-world applications. The RISC-V machine learning ecosystem is evaluated, from instruction set extensions and core implementations to compiler optimizations and deployment strategies. Key contributions include a unified taxonomy of RISC-V ML implementations, a comparative analysis of performance and design trade-offs, an evaluation of software toolchain maturity, and the identification of emerging trends in instruction set extensions and specialized accelerators. Findings reveal progress in energy efficiency, specialized instruction development, and framework integration, while highlighting challenges in standardization, verification complexity, and ecosystem fragmentation. The analysis proposes four research directions to address current limitations: specialized neural processing extensions, adaptive and modular processor architectures, security frameworks, and energy-efficient multi-domain architectures. These directions provide a roadmap for advancing RISC-V as a foundational platform for next-generation machine learning systems.

Machine Learning (cs.LG); Hardware Architecture (cs.AR)

arXiv:2609.20677 [cs.LG]

(or arXiv:2609.20677v1 [cs.LG] for this version)

https://doi.org/10.48550/arXiv.2609.20677 Focus to learn more arXiv-issued DOI via DataCite (pending registration)

https://doi.org/10.1007/s11227-026-08463-z Focus to learn more DOI(s) linking to related resources

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