RAM-Net: Linear-Time Sequence Modeling with Sparsely Addressable State

Abstract:Linear attention offers an efficient alternative to full attention with a fixed-size recurrent state. However, this state is shared by all tokens, so information from distinct tokens becomes superposed within it and produces inter-token interference that degrades long-range fine-grained recall. To address this issue, we propose RAM-Net, which replaces dense access to a shared state with sparse address-based access. RAM-Net organizes the recurrent state as a fixed-size array of independent slots and uses an Address Decoder that maps each key or query into a sparse address, selecting a small subset of slots to write to or read from at each step. This design directs tokens with non-overlapping addresses to disjoint slots, suppressing inter-token interference, while keeping per-step state access dependent only on the number of selected slots rather than the total state size. Empirically, RAM-Net outperforms strong recurrent baselines on fine-grained long-range retrieval and achieves the lowest perplexity with competitive commonsense reasoning. It does so while accessing fewer state elements per step than all baselines, e.g., $8\times$ fewer than Mamba2.

Accepted at NeurIPS 2026. Project page: this https URL

Machine Learning (cs.LG); Computation and Language (cs.CL)

arXiv:2602.11958 [cs.LG]

(or arXiv:2602.11958v2 [cs.LG] for this version)

https://doi.org/10.48550/arXiv.2602.11958 Focus to learn more arXiv-issued DOI via DataCite

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