LOADBench: A Large Open Analog Dataset and Benchmark for Machine Learning in IC Design

Abstract:Machine learning (ML) for analog IC design is constrained by limited open data and the absence of standardized evaluation: results reported in different papers are typically obtained on bespoke, often closed, datasets and with ad-hoc metrics, leaving comparisons across methods unreliable. We address both gaps with a large opensource dataset and a suite of standardized benchmarks. The dataset contains more than 100 operational amplifier (opamp) topologies (1-, 2-, and 3-stage) in the SkyWater130 PDK, each shipped with structural and functional annotations, topology-specific sizing constraints (symmetry and sizing rules), an Ngspice testbench, and a multi-objective NSGA-II sizing run producing around 103 Pareto-optimal and 106 intermediate sizing-performance pairs per topology. On top of this data we define six benchmark tasks with precise protocols: inverse sizing, topology selection, sub-circuit classification, structural circuit generation, Pareto-membership prediction, and multi-objective optimization. Thus, the data presented here constitutes the most comprehensive dataset for ML development in over four decades of analog IC design automation. The dataset, ground-truth annotations, and reference implementations of the metric-defining routines are released under an open license, enabling reproducible and directly comparable evaluation across heterogeneous analog design automation methods.

Artificial Intelligence (cs.AI)

arXiv:2610.21591 [cs.AI]

(or arXiv:2610.21591v1 [cs.AI] for this version)

https://doi.org/10.48550/arXiv.2610.21591 Focus to learn more arXiv-issued DOI via DataCite (pending registration)

https://doi.org/10.1145/3831599.3840321 Focus to learn more DOI(s) linking to related resources

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