IBM stacks silicon wafers for a denser, faster chip

IBM is developing a new approach to chip design with its nanostack architecture, achieving nearly 100 billion transistors on a chip the size of a fingernail. This innovation builds transistors upward, rather than outward, overcoming the spatial limits of traditional scaling and changing how semiconductors are manufactured. Initial projections suggest nanostack chips will consume 70% less energy and run 50% faster than existing 2nm node technologies, benefiting applications from AI to mobile devices. The nanostack architecture reconfigures transistor arrangement, allowing for the stacking of nanosheets and a departure from traditional two-dimensional scaling limitations. IBM’s approach fundamentally alters how transistors are built, moving beyond the established X and Y axes to incorporate the Z axis for increased density and performance. This shift represents a significant change in logic technology scaling, with projections indicating the potential to extend these advancements to 2040. The architecture’s flexibility allows for the strategic layering of transistor types; Tenko Yamashita, senior manager for advanced logic pathfinding technology at IBM Research, explained, “You can put…