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This deployment marks a critical infrastructure milestone by physically co-locating IBM's 120-qubit processor with AMD-powered HPC systems to eliminate latency bottlenecks in real-time quantum error correction. By enabling sub-millisecond feedback loops, the platform directly addresses the hardware requirements necessary for scaling fault-tolerant logical qubits and advancing multi-layered error-correcting codes.

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IBM, ORNL, and AMD Deploy Co-Located Quantum Error Correction Platform in Poughkeepsie

Quantum Computing ReportNovember 6, 20263 min read

IBM, ORNL, and AMD have launched a co-located quantum error correction (QEC) platform in Poughkeepsie, combining IBM's 120-qubit Quantum Nighthawk r2 processor with ORNL's Umbra HPC system (powered by AMD) to eliminate network latency. This setup enables real-time error correction for fault-tolerant quantum computing, focusing on scaling multi-layered error-correcting codes and targeting applications in condensed matter physics and neutron scattering analysis. The initiative supports IBM's roadmap for its future fault-tolerant system, IBM Quantum Starling. The post IBM, ORNL, and AMD Deploy Co-Located Quantum Error Correction Platform in Poughkeepsie appeared first on Quantum Computing Report.

Hardware and supercomputing leaders IBM (NYSE: IBM), the Quantum Science Center (QSC) at Oak Ridge National Laboratory (ORNL), and AMD (NASDAQ: AMD) have launched a dedicated quantum error correction (QEC) co-design platform at IBM’s facility in Poughkeepsie, New York. Designed to eliminate network latency bottlenecks…

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