aiqbench analysis
This research presents novel graph-aware reductions and symmetry pruning techniques to accelerate static qubit allocation on sparse quantum devices, achieving significant speedups in certifying optimal mappings without relying on heavy distributed frameworks. By integrating circuit-independent device profiles with efficient search engineering, the study demonstrates a substantial reduction in computational resources required for exact optimization of quadratic assignment problems inherent to physical layer mapping.
Graph-Aware Exact Branch-and-Bound with Device Profiles for Static Qubit Allocation
arXiv:2608.04058v1 Announce Type: new Abstract: Static qubit allocation maps a circuit's logical qubits to a sparse physical device while minimising an interaction-weighted physical-distance cost function, yielding a rectangular quadratic assignment problem. Existing work combines strong lower bounds with distributed branch-and-bound. We integrate graph-aware exact reductions with an engineering bundle for a lightweight assignment-bound path: unavoidable assigned-cost filtering, incrementally maintained root-orbit and prefix-stabilizer symmetry pruning, conditioned parent-LAP screening, and circuit-independent physical device profiles. On 21 relatively easy Melbourne instances and six Boeblingen instances completed by the GLB baseline, the final single-thread configuration provides geometric-mean speedups of 2.98x and 13.27x, respectively. With 60 threads on one shared-memory server, all instances in the final Boeblingen--Cairo experiment are certified optimal within half an hour, excluding one-time device-artifact construction. These results show that graph-aware node processing and engineering the search process substantially reduce the resources required for exact allocation.
Abstract:Static qubit allocation maps a circuit's logical qubits to a sparse physical device while minimising an interaction-weighted physical-distance cost function, yielding a rectangular quadratic assignment problem. Existing work combines strong lower bounds with distributed branch-and-bound. We integrate graph-aware exact reductions with an engineering bundle for a lightweight assignment-bound path: unavoidable assigned-cost filtering, incrementally maintained root-orbit and prefix-stabilizer symmetry pruning, conditioned parent-LAP screening, and circuit-independent physical device profiles. On 21 relatively easy Melbourne instances and six Boeblingen instances completed by the GLB baseline, the final single-thread configuration provides geometric-mean speedups of 2.98x and 13.27x, respectively. With 60 threads on one shared-memory server, all instances in the final Boeblingen--Cairo experiment are certified optimal within half an hour, excluding one-time device-artifact construction. These results show that graph-aware node processing and engineering the search process substantially reduce the resources required for exact allocation.
arXiv:2608.04058 [quant-ph]
(or arXiv:2608.04058v1 [quant-ph] for this version)
https://doi.org/10.48550/arXiv.2608.04058 Focus to learn more arXiv-issued DOI via DataCite
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