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The paper applies a graph neural network to a semiconductor manufacturing problem: splitting contact and via layouts into masks for multiple patterning combined with directed self-assembly. Its main contributions are a conflict graph that models DSA template edge-to-edge spacing, which prior methods ignored, and a GNN-driven local refinement step that claims better solution quality and faster convergence. For AI readers, the practical takeaway is a concrete case of learned graph models applied to a constrained combinatorial design task, though the reported gains are relative to unnamed baselines and need independent validation.
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GNN-Guided Local Refinement for Efficient Layout Decomposition with DSA-MP

arXiv2 min read

arXiv:2610.22214v1 Announce Type: new Abstract: Multiple patterning lithography (MPL) has been widely used to improve lithography resolution in advanced nodes, but it faces cost limits as feature sizes shrink. Directed self-assembly (DSA) offers a cost-effective complement, extending the resolution of optical lithography to sub-10 nm and beyond. Integrating DSA into MPL (DSA-MP) further enhances the resolution of contact/via patterning. Nevertheless, growing design complexity exposes the limits of existing decomposition methods, which struggle to balance solution quality and runtime, and neglect edge-to-edge spacing constraints of DSA templates, compromising manufacturability. To address these issues, we introduce a new conflict graph model capturing the previously overlooked constraints and develop a local refinement strategy powered by the graph neural network, enabling efficient and scalable layout decomposition. Experiments demonstrate that our method achieves higher solution quality with faster convergence than state-of-the-art methods, while maintaining robustness across layout scales, design styles, technology nodes, and varying mask counts.

Abstract:Multiple patterning lithography (MPL) has been widely used to improve lithography resolution in advanced nodes, but it faces cost limits as feature sizes shrink. Directed self-assembly (DSA) offers a cost-effective complement, extending the resolution of optical lithography to sub-10 nm and beyond. Integrating DSA into MPL (DSA-MP) further enhances the resolution of contact/via patterning. Nevertheless, growing design complexity exposes the limits of existing decomposition methods, which struggle to balance solution quality and runtime, and neglect edge-to-edge spacing constraints of DSA templates, compromising manufacturability. To address these issues, we introduce a new conflict graph model capturing the previously overlooked constraints and develop a local refinement strategy powered by the graph neural network, enabling efficient and scalable layout decomposition. Experiments demonstrate that our method achieves higher solution quality with faster convergence than state-of-the-art methods, while maintaining robustness across layout scales, design styles, technology nodes, and varying mask counts.

9 pages. Accepted at the IEEE/ACM International Conference on Computer-Aided Design (ICCAD 2026)

Artificial Intelligence (cs.AI)

arXiv:2610.22214 [cs.AI]

(or arXiv:2610.22214v1 [cs.AI] for this version)

https://doi.org/10.48550/arXiv.2610.22214 Focus to learn more arXiv-issued DOI via DataCite (pending registration)

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Full text under the publisher's open licence · 253 words

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