aiqbench analysis
This research introduces GPA, a graph neural network framework that significantly improves delay estimation accuracy in technology mapping by leveraging real post-mapping circuit data rather than abstract models. By fusing functional and timing views of circuit structures, the method achieves substantial performance gains over conventional heuristics and prior machine learning approaches without sacrificing area efficiency. The work represents a meaningful advancement in applying deep learning to optimize physical design workflows for semiconductor manufacturing.
GNN-based Path-aware multi-view Circuit Learning for Technology Mapping
arXiv:2601.14286v2 Announce Type: replace-cross Abstract: Traditional technology mapping suffers from systemic inaccuracies in delay estimation due to its reliance on abstract, technology-agnostic delay models that fail to capture the nuanced timing behavior behavior of real post-mapping circuits. To address this fundamental limitation, we introduce GPA(graph neural network (GNN)-based Path-Aware multi-view circuit learning), a novel GNN framework that learns precise, data-driven delay predictions by synergistically fusing three complementary views of circuit structure: And-Inverter Graphs (AIGs)-based functional encoding, post-mapping technology emphasizes critical timing paths. Trained exclusively on real cell delays extracted from critical paths of industrial-grade post-mapping netlists, GPA learns to classify cut delays with unprecedented accuracy, directly informing smarter mapping decisions. Evaluated on the 19 EPFL combinational benchmarks, GPA achieves 19.9%, 2.1% and 4.1% average delay reduction over the conventional heuristics methods (techmap, MCH) and the prior state-of-the-art ML-based approach SLAP, respectively-without compromising area efficiency.
Abstract:Traditional technology mapping suffers from systemic inaccuracies in delay estimation due to its reliance on abstract, technology-agnostic delay models that fail to capture the nuanced timing behavior behavior of real post-mapping circuits. To address this fundamental limitation, we introduce GPA(graph neural network (GNN)-based Path-Aware multi-view circuit learning), a novel GNN framework that learns precise, data-driven delay predictions by synergistically fusing three complementary views of circuit structure: And-Inverter Graphs (AIGs)-based functional encoding, post-mapping technology emphasizes critical timing paths. Trained exclusively on real cell delays extracted from critical paths of industrial-grade post-mapping netlists, GPA learns to classify cut delays with unprecedented accuracy, directly informing smarter mapping decisions. Evaluated on the 19 EPFL combinational benchmarks, GPA achieves 19.9%, 2.1% and 4.1% average delay reduction over the conventional heuristics methods (techmap, MCH) and the prior state-of-the-art ML-based approach SLAP, respectively-without compromising area efficiency.
Emerging Technologies (cs.ET); Machine Learning (cs.LG)
arXiv:2601.14286 [cs.ET]
(or arXiv:2601.14286v2 [cs.ET] for this version)
https://doi.org/10.48550/arXiv.2601.14286 Focus to learn more arXiv-issued DOI via DataCite
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Full text under the publisher's open licence · 234 words
