aiqbench analysis
This study identifies a critical error source in silicon spin-qubit architectures by linking three-dimensional electrostatics to qubit behavior during variational quantum eigensolvers. The findings reveal that exchange-based two-qubit gates are significantly more susceptible to gate-voltage noise than single-qubit rotations, providing essential data for improving fidelity in molecular simulation algorithms.
Gate-voltage noise limits accuracy of qubit calculations

New research published August 12, 2026, in Quantum Science and Technology reveals how fluctuations in gate-voltage noise significantly impact the accuracy of silicon spin-qubit calculations.
Researchers Xinning Wang, Bohdan Khromets, Zach Merino and Jonathan Baugh, affiliated with the Institute for Quantum Computing, University of Waterloo, and the Departments of Chemistry and Physics/Astronomy at the University of Waterloo, have identified a critical limitation in silicon spin-qubit technology. Their work demonstrates that gate-voltage noise significantly impacts the accuracy of variational quantum eigensolvers, a specific type of quantum algorithm used for tasks like molecular simulation. The data supporting this study are available upon reasonable request from the authors. Silicon spin qubits, a leading candidate for scalable quantum computing, face a critical limitation in their ability to accurately execute variational quantum eigensolvers (VQE), a hybrid quantum-classical algorithm used for…
Excerpt shown under the publisher's RSS terms · 110 words · full text and figures are on the publisher's site
Related coverage
Running Variational Quantum Eigensolver with Qiskit Aer on AMD Instinct
AMD · May 29, 2026

Noisy quantum cooling
Quantum Zeitgeist · Oct 13, 2026

Quantum Computers Need 100,000-Fold Performance Gain For Scientific Utility, Study Finds
The Quantum Insider · Sep 15, 2026
Impact of gate-voltage noise on silicon spin-qubit variational quantum eigensolvers
arXiv · Jun 9, 2026