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This paper outlines a roadmap for exchange-only spin qubits, bridging the gap between Noisy Intermediate-Scale Quantum (NISQ) devices and fault-tolerant systems through specific algorithmic benchmarks. It details how native error detection techniques can enhance performance on near-term hardware while providing resource estimates for simulating complex models like Fermi-Hubbard. These findings offer critical quantitative insights for scaling quantum chips and informing future hardware design choices in the spin-qubit ecosystem.
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From NISQ to Fault-Tolerance: Applications and Algorithmic Benchmarks for Spin Qubits

arXiv2 min read

arXiv:2609.07210v1 Announce Type: new Abstract: Motivated by recent breakthroughs in the development of spin-based quantum processing units based on exchange-only (EO) spin qubits, we provide a roadmap for the implementation of quantum algorithms on the EO platform, ranging from the NISQ to the fault-tolerant era. To provide an algorithm-driven perspective on the scaling of quantum chips, we consider a range of applications targeting different stages of hardware maturity and formulate requirements for a successful realization. We show that the compilation method Parity Twine perfectly complements the hardware's capabilities to perform tasks such as the quantum Fourier transform or QAOA. Furthermore, we describe an error detection technique native to Parity Twine, which EO qubits can leverage in a unique and advantageous way to improve algorithm performance. Finally, since both near-term algorithmic benchmarks and a long-term perspective can be found in digital quantum simulation, we specifically discuss the fermionic fast Fourier transform and the simulation of Fermi-Hubbard models. The latter is explicitly discussed in the context of quantum error correction and a partially fault-tolerant realization. By providing detailed resource estimates and identifying scaling bottlenecks on each level, our work offers a quantitative perspective on EO-based quantum computing and will inform future hardware design choices.

Abstract:Motivated by recent breakthroughs in the development of spin-based quantum processing units based on exchange-only (EO) spin qubits, we provide a roadmap for the implementation of quantum algorithms on the EO platform, ranging from the NISQ to the fault-tolerant era. To provide an algorithm-driven perspective on the scaling of quantum chips, we consider a range of applications targeting different stages of hardware maturity and formulate requirements for a successful realization. We show that the compilation method Parity Twine perfectly complements the hardware's capabilities to perform tasks such as the quantum Fourier transform or QAOA. Furthermore, we describe an error detection technique native to Parity Twine, which EO qubits can leverage in a unique and advantageous way to improve algorithm performance. Finally, since both near-term algorithmic benchmarks and a long-term perspective can be found in digital quantum simulation, we specifically discuss the fermionic fast Fourier transform and the simulation of Fermi-Hubbard models. The latter is explicitly discussed in the context of quantum error correction and a partially fault-tolerant realization. By providing detailed resource estimates and identifying scaling bottlenecks on each level, our work offers a quantitative perspective on EO-based quantum computing and will inform future hardware design choices.

arXiv:2609.07210 [quant-ph]

(or arXiv:2609.07210v1 [quant-ph] for this version)

https://doi.org/10.48550/arXiv.2609.07210 Focus to learn more arXiv-issued DOI via DataCite (pending registration)

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Full text under the publisher's open licence · 288 words

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