aiqbench analysis
This research presents a method for implementing fully addressable, fault-tolerant two-qubit Clifford gates on specific quantum low-density parity check (qLDPC) codes using round-robin sparsification. By applying geometrically structured circuits to various code families like toric and hypergraph-product codes, the study demonstrates scalable logical error rates essential for practical quantum memory and computation. The work advances the hardware feasibility of utilizing qLDPC codes by solving the critical challenge of individual logical unit manipulation.
Fault-tolerant and fully addressable unitary logical gates via round-robin sparsification
arXiv:2610.03594v1 Announce Type: new Abstract: For quantum low-density parity check (qLDPC) codes, the ability to manipulate individual logical units of information, i.e. the use of addressable gates, enables maximal utility of their efficient encoding. We introduce explicit low-depth unitary circuits that realize fully addressable and fault-tolerant two-qubit Clifford gates for a subset of two-dimensional translationally invariant qLDPC codes. Our transversal unitaries are created by applying a geometrically structured sparsification procedure to round-robin circuits. We verify the general applicability of our protocol by proposing and numerically simulating a range of addressable CZs between toric, cyclic hypergraph-product, color, gross, and directional codes, demonstrating fault-tolerant memory-like logical error rate scaling.
Abstract:For quantum low-density parity check (qLDPC) codes, the ability to manipulate individual logical units of information, i.e. the use of addressable gates, enables maximal utility of their efficient encoding. We introduce explicit low-depth unitary circuits that realize fully addressable and fault-tolerant two-qubit Clifford gates for a subset of two-dimensional translationally invariant qLDPC codes. Our transversal unitaries are created by applying a geometrically structured sparsification procedure to round-robin circuits. We verify the general applicability of our protocol by proposing and numerically simulating a range of addressable CZs between toric, cyclic hypergraph-product, color, gross, and directional codes, demonstrating fault-tolerant memory-like logical error rate scaling.
arXiv:2610.03594 [quant-ph]
(or arXiv:2610.03594v1 [quant-ph] for this version)
https://doi.org/10.48550/arXiv.2610.03594 Focus to learn more arXiv-issued DOI via DataCite (pending registration)
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Full text under the publisher's open licence · 193 words
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