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This research presents a significant efficiency boost for fault-tolerant quantum computing by simplifying resource states in LDPC codes to cat states, enabling faster joint measurements of multiple logical qubits. Numerical simulations demonstrate substantial speed-ups over previous methods when measuring commuting operators and executing random Clifford circuits within the walking cat architecture. The protocol's applicability extends beyond standard gates to non-Clifford operations like Toffoli gates, offering a practical pathway toward scalable quantum processors with reduced overhead.
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Fast logical operations in quantum LDPC codes using simple resource states

arXiv3 min read

arXiv:2607.16166v2 Announce Type: replace Abstract: Quantum LPDC codes provide a substantial reduction in qubit overhead required for fault-tolerant quantum computation compared to surface code, thanks to their high encoding rate. However, operating simultaneously on multiple logical qubits encoded in the same block is more challenging and may slow down logical operations. Prior work addresses this problem by designing complex resource states to perform logical measurements in LDPC codes. Here, we propose an approach that only consumes cat states. Whereas previous work on cat-based measurements focuses on a single logical measurement, we design a protocol for the joint measurement of $\ell$ commuting logical operators. The key ingredient is the design of a scheduler code determining the measurement sequence and allowing for the decoding of all logical measurement outcomes. Numerical simulations with the LDPC codes Q70 and Q102 of the walking cat architecture show a speed-up of nearly $3\times$ over Viterbi measurements for the measurement of $\ell=20$ commuting logical operators. Combining our fast logical measurements with a new variant of the CliNR partial error correction scheme, we achieve a speed-up of up to $74\times$ for random Clifford circuits. Our approach also applies to non-Clifford gates, producing a speed-up of up to $5\times$ for Toffoli gates.

Abstract:Quantum LPDC codes provide a substantial reduction in qubit overhead required for fault-tolerant quantum computation compared to surface code, thanks to their high encoding rate. However, operating simultaneously on multiple logical qubits encoded in the same block is more challenging and may slow down logical operations. Prior work addresses this problem by designing complex resource states to perform logical measurements in LDPC codes. Here, we propose an approach that only consumes cat states. Whereas previous work on cat-based measurements focuses on a single logical measurement, we design a protocol for the joint measurement of $\ell$ commuting logical operators. The key ingredient is the design of a scheduler code determining the measurement sequence and allowing for the decoding of all logical measurement outcomes. Numerical simulations with the LDPC codes Q70 and Q102 of the walking cat architecture show a speed-up of nearly $3\times$ over Viterbi measurements for the measurement of $\ell=20$ commuting logical operators. Combining our fast logical measurements with a new variant of the CliNR partial error correction scheme, we achieve a speed-up of up to $74\times$ for random Clifford circuits. Our approach also applies to non-Clifford gates, producing a speed-up of up to $5\times$ for Toffoli gates.

arXiv:2607.16166 [quant-ph]

(or arXiv:2607.16166v2 [quant-ph] for this version)

https://doi.org/10.48550/arXiv.2607.16166 Focus to learn more arXiv-issued DOI via DataCite

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Full text under the publisher's open licence · 287 words

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