Dimensionality reduction for closed-loop quantum gate calibration

Abstract:Numerical gate design typically makes use of high-dimensional parameterizations enabling sophisticated, highly expressive control pulses. Developing efficient experimental calibration methods for such gates is a long-standing challenge in quantum control, as on-device calibration requires the optimization of noisy experimental data over high-dimensional parameter spaces. To improve the efficiency of calibrations, we present a systematic method based on SVD stacking for reducing the dimensionality of the parameter space traversed in gate calibration, starting from an arbitrary high-dimensional pulse representation. We use this approach to design and calibrate an $X_{\pi/2}$ gate robust against amplitude and detuning errors, as well as an $X_{\pi/2}$ gate robust against coherent errors due to a spectator qubit.

arXiv:2412.05230 [quant-ph]

(or arXiv:2412.05230v2 [quant-ph] for this version)

https://doi.org/10.48550/arXiv.2412.05230 Focus to learn more arXiv-issued DOI via DataCite

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