aiqbench analysis
This paper proposes a hybrid digital-analog architecture for classical quantum emulators, aiming to overcome bandwidth and scaling bottlenecks inherent in current FPGA-based systems by leveraging analog signal properties like voltage RMS, frequency, and phase. While the approach offers a cost-effective solution at approximately $5 per qubit, its practical utility remains constrained by precision limits that prevent scaling beyond tens of qubits without significant improvements in analog circuit performance. The work represents a meaningful theoretical advancement for classical simulation techniques but does not yet deliver a functional quantum advantage over existing hardware.
Designing a Hybrid Digital / Analog Quantum Physics Emulator as Open Hardware
arXiv:2302.00821v4 Announce Type: replace Abstract: Existing approaches to emulating quantum computing algorithms using classical electronic hardware are limited by exponential scaling limitations in space, such as circuit size, or time, such as runtime or bandwidth. We introduce a scheme for representing quantum information using analog signals that lessens the bandwidth limitation problem (in certain regimes) seen in existing approaches [1, 2] by taking full advantage of the ability of analog signals to encode information using RMS voltage as well as frequency and phase. We introduce the mathematical framework for this representation, which separates the information relevant for measurement in the computational basis from information that is not relevant to it. We introduce circuits that take advantage of this separation of concerns to achieve simplifications, for working with quantum information in this representation. We argue that it is comparatively very inexpensive (as low as ~$5.00 / qubit) to outmatch the computing capabilities of existing FPGA based emulators [3], though scaling beyond tens of qubits is still impractical due to constraints of analog hardware module precision. However, our approach opens the door to a new avenue by which classical emulators can hope to improve: by improving on analog electronic circuit performance.
Abstract:Existing approaches to emulating quantum computing algorithms using classical electronic hardware are limited by exponential scaling limitations in space, such as circuit size, or time, such as runtime or bandwidth. We introduce a scheme for representing quantum information using analog signals that lessens the bandwidth limitation problem (in certain regimes) seen in existing approaches [1, 2] by taking full advantage of the ability of analog signals to encode information using RMS voltage as well as frequency and phase. We introduce the mathematical framework for this representation, which separates the information relevant for measurement in the computational basis from information that is not relevant to it. We introduce circuits that take advantage of this separation of concerns to achieve simplifications, for working with quantum information in this representation. We argue that it is comparatively very inexpensive (as low as ~$5.00 / qubit) to outmatch the computing capabilities of existing FPGA based emulators [3], though scaling beyond tens of qubits is still impractical due to constraints of analog hardware module precision. However, our approach opens the door to a new avenue by which classical emulators can hope to improve: by improving on analog electronic circuit performance.
arXiv:2302.00821 [quant-ph]
(or arXiv:2302.00821v4 [quant-ph] for this version)
https://doi.org/10.48550/arXiv.2302.00821 Focus to learn more arXiv-issued DOI via DataCite
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Full text under the publisher's open licence · 283 words
