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This paper introduces GALA codes, a novel family of quantum error-correcting codes specifically engineered for reconfigurable neutral atom arrays with limited optical control. By leveraging group-action lifts, the design achieves a rate-1/2 encoding efficiency and provides explicit logical instruction sets compatible with acousto-optic deflectors, directly addressing hardware constraints that often limit practical fault tolerance. The work demonstrates significant overhead reduction and simplified move schedules for syndrome extraction on near-term quantum devices.
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Designer Codes from GALA: Compact, Self-Dual, and Rate-1/2 QEC on Reconfigurable Atom Arrays

arXiv3 min read

arXiv:2608.07431v2 Announce Type: replace Abstract: Achieving useful fault-tolerant applications requires co-designing the quantum error-correcting code for footprint, logical instruction set, and hardware compatibility simultaneously. Recent breakthroughs in ultra-high-rate codes have the potential to reduce footprint of large scale quantum applications but their practical utility is limited without an addressable logical instruction set and efficient implementation on near term hardware. Reconfigurable neutral atom arrays, for example, support only hundreds of qubits with constrained reconfigurability from a few crossed acousto-optic deflectors (AOD). We introduce the GALA codes, or Group-Action Lifts with Active orthogonality, that allows such co-design by construction. GALA lifts over a product group $G = H_k \times C_m$ (or $H_k \ltimes C_m^k$); the small non-abelian factor $H_k$ supplies active orthogonality that improves qubit overhead, reaching 1/2 encoding rate with above-weight distance, while the large abelian factor $C_m$ supplies symmetries that give code automorphisms and explicit, simple AOD move schedules. Logical addressibility and hardware compatibility follow directly from construction, rather than verified post-hoc. The GALA family contains several known rate-1/2 Kasai codes of Ref.[arXiv:2601.08824, arXiv:2604.16209] while exposing simpler parameter bounds, logical operations, and ZX-dual variants with AOD-compatible fold-transversal Clifford gates. In particular, we find a compact self-dual $[[132,30,12]]$ with $1.0^{+0.9}_{-0.6}\times 10^{-9}$ per-round per-qubit logical error rate at $10^{-3}$ physical error rate, equipped with 3.1 ms syndrome-extraction cycles and an addressable logical instruction set; a ZX-dual, girth-6, rate-1/2 $[[672,336,12]]$ with a 6.76 ms cycles; and barrier-breaking $[[1752,880,14]]$ and $[[2232,1120,16]]$ smaller than previously known hardware-compatible rate-1/2 codes.

Abstract:Achieving useful fault-tolerant applications requires co-designing the quantum error-correcting code for footprint, logical instruction set, and hardware compatibility simultaneously. Recent breakthroughs in ultra-high-rate codes have the potential to reduce footprint of large scale quantum applications but their practical utility is limited without an addressable logical instruction set and efficient implementation on near term hardware. Reconfigurable neutral atom arrays, for example, support only hundreds of qubits with constrained reconfigurability from a few crossed acousto-optic deflectors (AOD). We introduce the GALA codes, or Group-Action Lifts with Active orthogonality, that allows such co-design by construction. GALA lifts over a product group $G = H_k \times C_m$ (or $H_k \ltimes C_m^k$); the small non-abelian factor $H_k$ supplies active orthogonality that improves qubit overhead, reaching 1/2 encoding rate with above-weight distance, while the large abelian factor $C_m$ supplies symmetries that give code automorphisms and explicit, simple AOD move schedules. Logical addressibility and hardware compatibility follow directly from construction, rather than verified post-hoc. The GALA family contains several known rate-1/2 Kasai codes of Ref.[arXiv:2601.08824, arXiv:2604.16209] while exposing simpler parameter bounds, logical operations, and ZX-dual variants with AOD-compatible fold-transversal Clifford gates. In particular, we find a compact self-dual $[[132,30,12]]$ with $1.0^{+0.9}_{-0.6}\times 10^{-9}$ per-round per-qubit logical error rate at $10^{-3}$ physical error rate, equipped with 3.1 ms syndrome-extraction cycles and an addressable logical instruction set; a ZX-dual, girth-6, rate-1/2 $[[672,336,12]]$ with a 6.76 ms cycles; and barrier-breaking $[[1752,880,14]]$ and $[[2232,1120,16]]$ smaller than previously known hardware-compatible rate-1/2 codes.

arXiv:2608.07431 [quant-ph]

(or arXiv:2608.07431v2 [quant-ph] for this version)

https://doi.org/10.48550/arXiv.2608.07431 Focus to learn more arXiv-issued DOI via DataCite

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