aiqbench analysis
CascadeLUT addresses the critical bottleneck of data movement in bandwidth-constrained FPGA environments by introducing an information-ordered streaming inference framework for LUT-based models. This approach eliminates pipeline stalls caused by full-sample buffering, enabling deterministic processing with significant reductions in latency and energy consumption without requiring runtime branching logic. The work represents a key advancement in optimizing hardware-software co-design specifically for efficient neural network deployment on reconfigurable fabrics.
CascadeLUT: Information-Ordered Streaming Inference for Bandwidth-Constrained FPGAs
arXiv:2608.00720v1 Announce Type: cross Abstract: Mapping neural networks to FPGAs enables low-latency, energy-efficient inference, particularly for lookup table (LUT)-based models that eliminate multipliers and map directly to reconfigurable fabric. While prior work achieves high compute efficiency, it typically assumes full-sample availability, causing pipeline stalls in bandwidth-limited streaming scenarios. Here, the bottleneck shifts from computation to data movement, as large input transfers limit throughput and energy efficiency. We present CascadeLUT, an information-structured inference framework organized around bandwidth constraints. Instead of buffering the full input, features are partitioned into ordered subsets and predictions are progressively refined as subsets arrive. The cascade statically controls which layers consume incoming features, enabling deterministic streaming inference without runtime branching. By co-designing feature scheduling with hardware dataflow, CascadeLUT reduces data movement while maintaining accuracy. Across datasets, it achieves 4.0 to 12.5 times lower latency, 3.0 to 5.0 times higher throughput and up to 13.8 times lower energy/sample than prior LUT baselines, using 1.2 to 4.4 times the LUTs of the smallest DWN baseline per task. We also demonstrate on-device input quantization integrated with LUT-based inference and present end-to-end FPGA results on real-world workloads, with 5 times reductions in quantization overhead.
Abstract:Mapping neural networks to FPGAs enables low-latency, energy-efficient inference, particularly for lookup table (LUT)-based models that eliminate multipliers and map directly to reconfigurable fabric. While prior work achieves high compute efficiency, it typically assumes full-sample availability, causing pipeline stalls in bandwidth-limited streaming scenarios. Here, the bottleneck shifts from computation to data movement, as large input transfers limit throughput and energy efficiency. We present CascadeLUT, an information-structured inference framework organized around bandwidth constraints. Instead of buffering the full input, features are partitioned into ordered subsets and predictions are progressively refined as subsets arrive. The cascade statically controls which layers consume incoming features, enabling deterministic streaming inference without runtime branching. By co-designing feature scheduling with hardware dataflow, CascadeLUT reduces data movement while maintaining accuracy. Across datasets, it achieves 4.0 to 12.5 times lower latency, 3.0 to 5.0 times higher throughput and up to 13.8 times lower energy/sample than prior LUT baselines, using 1.2 to 4.4 times the LUTs of the smallest DWN baseline per task. We also demonstrate on-device input quantization integrated with LUT-based inference and present end-to-end FPGA results on real-world workloads, with 5 times reductions in quantization overhead.
To appear in the proceedings of the 36th International Conference on Field-Programmable Logic and Applications (FPL 2026). 6 pages, 2 figures
Hardware Architecture (cs.AR); Machine Learning (cs.LG)
arXiv:2608.00720 [cs.AR]
(or arXiv:2608.00720v1 [cs.AR] for this version)
https://doi.org/10.48550/arXiv.2608.00720 Focus to learn more arXiv-issued DOI via DataCite (pending registration)
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Full text under the publisher's open licence · 306 words
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