aiqbench analysis
This research presents a novel coherent CNOT gate scheme for cat qubits designed to preserve their inherent exponential noise bias during logical operations. By relying solely on unitary operations rather than engineered dissipation, the method avoids common non-idealities while enabling high-fidelity memory in the megaquop regime with realistic component lifetimes. The work addresses a critical bottleneck in hardware-efficient quantum error correction by maintaining robustness against phase flips without sacrificing bit-flip protection during gate execution.
Bias-preserving cat-cat CNOT gate via vacuum-conditional beam-splitter
arXiv:2607.22852v1 Announce Type: new Abstract: Cat qubits can exhibit strong noise bias due to their exponentially enhanced bit-flip times and only polynomially reduced phase-flip times with increasing photon number, which makes them attractive candidates for hardware-efficient quantum error correction. However, it is difficult to maintain this strong noise bias in logical operations such as CNOT gates between cats. Here, we propose a coherent CNOT gate scheme between two dissipative cats that preserves the exponential noise bias. The proposed gate relies only on unitary operations, which avoids the non-idealities associated with many existing gate schemes that rely on engineered dissipations. Assuming good component lifetimes and precise nonlinearity engineering, the proposed gate can enable logical memory in the megaquop regime (logical error rates < 10^-6) with a distance-7 repetition code consisting of 13 cat qubits.
Abstract:Cat qubits can exhibit strong noise bias due to their exponentially enhanced bit-flip times and only polynomially reduced phase-flip times with increasing photon number, which makes them attractive candidates for hardware-efficient quantum error correction. However, it is difficult to maintain this strong noise bias in logical operations such as CNOT gates between cats. Here, we propose a coherent CNOT gate scheme between two dissipative cats that preserves the exponential noise bias. The proposed gate relies only on unitary operations, which avoids the non-idealities associated with many existing gate schemes that rely on engineered dissipations. Assuming good component lifetimes and precise nonlinearity engineering, the proposed gate can enable logical memory in the megaquop regime (logical error rates < 10^-6) with a distance-7 repetition code consisting of 13 cat qubits.
arXiv:2607.22852 [quant-ph]
(or arXiv:2607.22852v1 [quant-ph] for this version)
https://doi.org/10.48550/arXiv.2607.22852 Focus to learn more arXiv-issued DOI via DataCite (pending registration)
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Full text under the publisher's open licence · 219 words
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