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This research introduces DeepSeq3, a hierarchical graph neural network framework designed to overcome scalability limits in Electronic Design Automation (EDA) by explicitly modeling temporal dynamics in sequential circuits. By combining fine-grained combinational subgraphs with high-level register-transfer structures, the model achieves an 18% reduction in bounded model checking time while maintaining correctness guarantees. The work represents a significant advancement in applying advanced machine learning techniques to optimize core hardware verification tasks.
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Beyond Flat Netlist: Hierarchical Graph Representation Learning for Scalable Analysis of Sequential Circuits

arXiv2 min read

arXiv:2608.28188v1 Announce Type: cross Abstract: Circuit Representation Learning (CRL) offers a powerful paradigm to guide and optimize core Electronic Design Automation (EDA) tasks, but its practical adoption is hindered by the immense scale of industrial netlists and a failure to explicitly model register-level temporal dynamics. To overcome these barriers, we introduce DeepSeq3, a novel hierarchical framework that abstracts circuits into a two-level representation: fine-grained combinational subgraphs partitioned by flip-flops (FFs), and a high-level Super-Node Graph (SNG) that models the register-transfer structure. A dual Graph Neural Network (GNN) architecture learns representations at both levels, capturing local Boolean logic and global state transitions. Crucially, we introduce a state-centric pre-training scheme that predicts the reachability between FF states, endowing the model with a deep understanding of temporal behavior. Demonstrated on large-scale benchmarks, DeepSeq3's approach yields superior scalability and richer representations, reducing bounded model checking (BMC) solving time by 18% while guaranteeing correctness.

Abstract:Circuit Representation Learning (CRL) offers a powerful paradigm to guide and optimize core Electronic Design Automation (EDA) tasks, but its practical adoption is hindered by the immense scale of industrial netlists and a failure to explicitly model register-level temporal dynamics. To overcome these barriers, we introduce DeepSeq3, a novel hierarchical framework that abstracts circuits into a two-level representation: fine-grained combinational subgraphs partitioned by flip-flops (FFs), and a high-level Super-Node Graph (SNG) that models the register-transfer structure. A dual Graph Neural Network (GNN) architecture learns representations at both levels, capturing local Boolean logic and global state transitions. Crucially, we introduce a state-centric pre-training scheme that predicts the reachability between FF states, endowing the model with a deep understanding of temporal behavior. Demonstrated on large-scale benchmarks, DeepSeq3's approach yields superior scalability and richer representations, reducing bounded model checking (BMC) solving time by 18% while guaranteeing correctness.

Machine Learning (cs.LG); Artificial Intelligence (cs.AI); Hardware Architecture (cs.AR)

arXiv:2608.28188 [cs.LG]

(or arXiv:2608.28188v1 [cs.LG] for this version)

https://doi.org/10.48550/arXiv.2608.28188 Focus to learn more arXiv-issued DOI via DataCite (pending registration)

https://doi.org/10.1145/3770743.3803902 Focus to learn more DOI(s) linking to related resources

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Full text under the publisher's open licence · 254 words

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