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This article introduces BBOPlace-Bench, a new standardized framework designed to evaluate black-box optimization algorithms specifically for semiconductor chip placement tasks. By integrating diverse problem formulations and algorithm families like genetic algorithms and Bayesian optimization, it addresses the historical lack of unified benchmarks in this niche area of hardware design automation. The benchmark aims to improve efficiency and scalability over traditional analytical methods by providing a modular platform for researchers to test and compare their approaches against established baselines.
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BBOPlace-Bench: Benchmarking Black-Box Optimization for Chip Placement

arXiv3 min read

arXiv:2510.23472v2 Announce Type: replace-cross Abstract: Chip placement is a vital stage in modern chip design, and black-box optimization (BBO) has been applied to it for decades. Early BBO efforts, however, were limited by immature problem formulations and inefficient algorithm designs, leading to worse efficiency, quality, and scalability than mainstream analytical methods. Recent advances in BBO have shown strong potential, but a unified, BBO-specific benchmark for thoroughly assessing various problem formulations and BBO algorithms is lacking. To fill this gap, we propose BBOPlace-Bench, the first benchmark tailored for evaluating and developing BBO algorithms for chip placement. It integrates three BBO problem formulations and offers a modular, flexible framework that enables users to seamlessly implement, test, and compare their own algorithms. It aggregates representative modern chip cases and standardizes their formats, providing uniform and comprehensive information to support BBO optimization. Moreover, it integrates representative BBO algorithm families, including simulated annealing, population-based search (including GA, CMA-ES, and PSO), and Bayesian optimization, and systematically evaluates their performance across different problem formulations using key chip-placement metrics. We position these experiments primarily as illustrative case studies under a shared evaluation protocol, including common benchmark instances, metric definitions, evaluation pipeline, and search budgets. Under this protocol, some BBO configurations (e.g., GA under the mask-guided optimization formulation) are competitive with representative analytical and reinforcement learning baselines. BBOPlace-Bench not only facilitates the development of efficient BBO-driven solutions for chip placement but also broadens the practical application scenarios urgently needed by the BBO community.

Abstract:Chip placement is a vital stage in modern chip design, and black-box optimization (BBO) has been applied to it for decades. Early BBO efforts, however, were limited by immature problem formulations and inefficient algorithm designs, leading to worse efficiency, quality, and scalability than mainstream analytical methods. Recent advances in BBO have shown strong potential, but a unified, BBO-specific benchmark for thoroughly assessing various problem formulations and BBO algorithms is lacking. To fill this gap, we propose BBOPlace-Bench, the first benchmark tailored for evaluating and developing BBO algorithms for chip placement. It integrates three BBO problem formulations and offers a modular, flexible framework that enables users to seamlessly implement, test, and compare their own algorithms. It aggregates representative modern chip cases and standardizes their formats, providing uniform and comprehensive information to support BBO optimization. Moreover, it integrates representative BBO algorithm families, including simulated annealing, population-based search (including GA, CMA-ES, and PSO), and Bayesian optimization, and systematically evaluates their performance across different problem formulations using key chip-placement metrics. We position these experiments primarily as illustrative case studies under a shared evaluation protocol, including common benchmark instances, metric definitions, evaluation pipeline, and search budgets. Under this protocol, some BBO configurations (e.g., GA under the mask-guided optimization formulation) are competitive with representative analytical and reinforcement learning baselines. BBOPlace-Bench not only facilitates the development of efficient BBO-driven solutions for chip placement but also broadens the practical application scenarios urgently needed by the BBO community.

Machine Learning (cs.LG); Artificial Intelligence (cs.AI); Hardware Architecture (cs.AR); Neural and Evolutionary Computing (cs.NE)

arXiv:2510.23472 [cs.LG]

(or arXiv:2510.23472v2 [cs.LG] for this version)

https://doi.org/10.48550/arXiv.2510.23472 Focus to learn more arXiv-issued DOI via DataCite

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Full text under the publisher's open licence · 342 words

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