Back to the Future: Rethinking EDA Infrastructure for Agentic Systems in Chip Design Verification

Abstract:The unprecedented computational scale of modern artificial intelligence depends on complex, multi-billion-transistor Systems-on-Chip, yet the workflows that verify these chips remain stubbornly manual. Although Large Language Models (LLMs) have made rapid inroads into Electronic Design Automation (EDA), approximately 74.6% of existing studies target static Register-Transfer Level (RTL) code generation, leaving post-simulation verification and interactive waveform debugging largely untouched. We introduce Back-to-the-Future (BTTF), an end-to-end agentic framework that closes this infrastructural gap. BTTF distills massive, unstructured simulation dumps into a normalized relational SQLite database and couples it with a collaborative multi-agent orchestration engine that translates natural-language verification queries into schema-aware SQL while correlating signal anomalies with versioned RTL repositories. Across a 150-query benchmark, BTTF attains 95.33% execution accuracy, charting a practical path toward autonomous EDA verification.

Artificial Intelligence (cs.AI)

arXiv:2610.06790 [cs.AI]

(or arXiv:2610.06790v1 [cs.AI] for this version)

https://doi.org/10.48550/arXiv.2610.06790 Focus to learn more arXiv-issued DOI via DataCite (pending registration)

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