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This partnership advances the hardware infrastructure required for fault-tolerant quantum computing by standardizing low-latency interfaces for quantum error correction on Agilex FPGAs. By providing an open-source reference design, the collaboration lowers barriers to entry for developers building control stacks across various qubit modalities. Simultaneously, the integration of native post-quantum cryptography secures classical edge infrastructure against future decryption threats, addressing both immediate and long-term security needs in quantum ecosystems.
Source coveringQuantum Computing Report
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Altera and Riverlane Partner on QEC Interfaces for Agilex FPGAs Following Post-Quantum Security Rollout

Quantum Computing Report2 min read

Altera and Riverlane have partnered to optimize quantum error correction (QEC) interfaces for Altera's Agilex FPGAs, enabling real-time QEC data movement and low-latency control. This collaboration, which includes an open-source QEC Interface (QECi) protocol, aims to standardize data exchange between quantum control electronics and QEC decoders. This initiative complements Altera's recent rollout of Post-Quantum Cryptography (PQC) support in its Agilex 3 and 5 FPGAs, establishing a dual strategy to secure classical infrastructure against quantum threats and provide control fabric for quantum computing. The post Altera and Riverlane Partner on QEC Interfaces for Agilex FPGAs Following Post-Quantum Security Rollout appeared first on Quantum Computing Report.

FPGA provider Altera (an Intel company) and quantum error correction (QEC) specialist Riverlane have announced a partnership to optimize real-time QEC data movement and low-latency control logic across Altera’s Agilex® FPGA portfolio. Under…

Excerpt shown under the publisher's RSS terms · 33 words · full text and figures are on the publisher's site

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