aiqbench analysis
This research addresses the scalability bottleneck in detecting hardware trojans within massive System-on-Chip (SoC) designs by leveraging And-Inverter Graphs for efficient Boolean network representation. By integrating symbolically enabled learning with Knowledge Graph Embeddings, the method achieves linear complexity scaling while effectively identifying rare structural anomalies indicative of malicious payloads. The approach represents a significant advancement in securing large-scale integrated circuits against sophisticated hardware-level attacks through advanced machine learning techniques.
ADVERSARIAL: And-Inverter Graph-Assisted Hardware Trojan Detection At Scale
arXiv:2607.23882v1 Announce Type: new Abstract: Modern System-on-Chip (SoCs) often contain hundreds of millions to tens of billions of gates, making existing Hardware Trojan (HT) detection methods impractical due to their immense scale. The proposed approach incorporates symbolically enabled learning by modeling flattened gate-level netlists as Boolean networks represented as And-Inverter Graphs (AIGs), where all internal nodes are 2-input AND gates and inversions reside on the edges. Each directed connection is expressed as a triple within a Knowledge Graph Embedding (KGE) framework, producing compact, constant-size per-node representations that retain multi-hop structural context. The AIG's bounded fan-in and uniform semantics ensure training and inference complexity scale linearly with edge count, addressing major scalability bottlenecks in HT detection. Symbolically enabled learning across deep datapaths enables the model to differentiate circuit structures from rare and functionally inconsistent connections that signify potential Trojan triggers and payloads. Experiments on large-scale SoC benchmarks demonstrate clear geometric separation between Trojan and benign nodes and practical scalability.
Abstract:Modern System-on-Chip (SoCs) often contain hundreds of millions to tens of billions of gates, making existing Hardware Trojan (HT) detection methods impractical due to their immense scale. The proposed approach incorporates symbolically enabled learning by modeling flattened gate-level netlists as Boolean networks represented as And-Inverter Graphs (AIGs), where all internal nodes are 2-input AND gates and inversions reside on the edges. Each directed connection is expressed as a triple within a Knowledge Graph Embedding (KGE) framework, producing compact, constant-size per-node representations that retain multi-hop structural context. The AIG's bounded fan-in and uniform semantics ensure training and inference complexity scale linearly with edge count, addressing major scalability bottlenecks in HT detection. Symbolically enabled learning across deep datapaths enables the model to differentiate circuit structures from rare and functionally inconsistent connections that signify potential Trojan triggers and payloads. Experiments on large-scale SoC benchmarks demonstrate clear geometric separation between Trojan and benign nodes and practical scalability.
9 pages, 5 figures, 3 tables. Accepted for publication at the IEEE/ACM International Conference on Computer-Aided Design (ICCAD 2026)
Machine Learning (cs.LG); Hardware Architecture (cs.AR); Cryptography and Security (cs.CR)
arXiv:2607.23882 [cs.LG]
(or arXiv:2607.23882v1 [cs.LG] for this version)
https://doi.org/10.48550/arXiv.2607.23882 Focus to learn more arXiv-issued DOI via DataCite (pending registration)
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Full text under the publisher's open licence · 273 words
