A Survey on Design Methodologies for Accelerating Deep Learning on Heterogeneous Architectures

Abstract:Given their increasing size and complexity, the need for efficient execution of deep neural networks has become increasingly pressing in the design of heterogeneous High-Performance Computing (HPC) and edge platforms, leading to a wide variety of proposals for specialized deep learning architectures and hardware accelerators. The design of such architectures and accelerators requires a multidisciplinary approach combining expertise from several areas, from machine learning to computer architecture, low-level hardware design, and approximate computing. Several methodologies and tools have been proposed to improve the process of designing accelerators for deep learning, aimed at maximizing parallelism and minimizing data movement to achieve high performance and energy efficiency. This paper critically reviews influential tools and design methodologies for Deep Learning accelerators, offering a wide perspective in this rapidly evolving field. This work complements surveys on architectures and accelerators by covering hardware-software co-design, automated synthesis, domain-specific compilers, design space exploration, modeling, and simulation, providing insights into technical challenges and open research directions.

Hardware Architecture (cs.AR); Artificial Intelligence (cs.AI)

arXiv:2311.17815 [cs.AR]

(or arXiv:2311.17815v3 [cs.AR] for this version)

https://doi.org/10.48550/arXiv.2311.17815 Focus to learn more arXiv-issued DOI via DataCite

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