A Hardware-Native Trapped-Ion Hybrid Qudit-Oscillator Instruction Set

Abstract:Scaling trapped-ion processors by adding ions remains challenging. A complementary route exploits the multilevel internal structure of each ion to increase the computational Hilbert space per ion. We introduce a hardware-native hybrid qudit-oscillator instruction set for a general d-level internal register coupled to bosonic modes and prove that three of its native operation families suffice for universality of one qudit coupled to several modes. Adding an entangling operation between ions extends universality to a connected register of several qudits. The architecture natively supports both phase-space and sideband instruction sets and is implemented in the open-source framework HybridLane. As a representative application, we reproduce the dissipative vibronic dynamics of a three-chromophore complex previously simulated on a hybrid qubit-oscillator superconducting platform. Moving from a one-qubit-per-state register to a single qudit stores the entire electronic manifold in one ion, so every electronic coupling becomes a local intra-ion transition and the lab-frame Hamiltonian compiles directly into the ISA. Under the stated sequential timing model from a 40Ca+ qudit processor, one Trotter step is projected to run about ten times faster on the qudit, with an average RMSE of approximately 1.1 percent against the published reference.

27 pages, 10 figures, 10 tables. Submitted to ACM Transactions on Quantum Computing

Quantum Physics (quant-ph); Hardware Architecture (cs.AR); Emerging Technologies (cs.ET)

arXiv:2610.13843 [quant-ph]

(or arXiv:2610.13843v1 [quant-ph] for this version)

https://doi.org/10.48550/arXiv.2610.13843 Focus to learn more arXiv-issued DOI via DataCite (pending registration)

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