rtl-property-inference
De la autor
Automatically infer formal correctness properties from Verilog/SystemVerilog RTL code and generate SystemVerilog Assertions (SVA). Identifies control-flow invariants (mutual exclusion, valid-ready handshakes, pipeline ordering, safety properties), liveness expectations, and temporal properties. Use when working with RTL designs that need formal property generation, when adding assertions to existing RTL, or when users ask to infer properties, generate assertions, or create formal specifications from hardware designs.
Instalare
npx skills add ArabelaTso/Skills-4-SE --skill rtl-property-inference -a claude-code
Se instalează în .claude/skills/rtl-property-inference/ · Fiecare comandă descarcă skill-ul direct de pe GitHub cu utilitarul open source skills.
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