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This work extends the hls4ml toolkit to support clock-driven Spiking Neural Network inference on conventional FPGAs, bridging the gap between neuromorphic concepts and synchronous hardware workflows. By enabling the deployment of PyTorch-trained SNNs with latencies around 34μs, the approach offers a practical pathway for integrating low-latency temporal processing into existing scientific real-time systems without requiring specialized asynchronous processors.
Spiking Neural Network inference on FPGAs with hls4ml
arXiv:2606.10008v1 Announce Type: cross Abstract: Spiking Neural Networks (SNNs) provide a naturally temporal machine-learning framework. Their neurons maintain an internal state and propagate information through discrete spikes, enabling low-latency temporal inference. Although SNNs are often associated with asynchronous neuromorphic processors, many scientific real-time inference systems rely on conventional synchronous field-programmable gate arrays (FPGAs) and high-level synthesis (HLS) workflows. In this paper we present an extension of hls4ml that enables clock-driven deployment of SNNs trained in pytorch onto FPGA firmware. We demonstrate the workflow using a dense quantised SNN trained on the Heidelberg Spiking Digits dataset where it achieves inference latencies of approximately $34\mu$s. We validate the generated design through software reference comparisons, HLS C simulation, HLS synthesis, export, and Vivado synthesis reports. This work opens up the hls4ml toolkit to neuromorphic computing, allowing streamlined optimisation, synthesis, and deployment of SNN models for real-time inference.
Abstract:Spiking Neural Networks (SNNs) provide a naturally temporal machine-learning framework. Their neurons maintain an internal state and propagate information through discrete spikes, enabling low-latency temporal inference. Although SNNs are often associated with asynchronous neuromorphic processors, many scientific real-time inference systems rely on conventional synchronous field-programmable gate arrays (FPGAs) and high-level synthesis (HLS) workflows. In this paper we present an extension of hls4ml that enables clock-driven deployment of SNNs trained in pytorch onto FPGA firmware. We demonstrate the workflow using a dense quantised SNN trained on the Heidelberg Spiking Digits dataset where it achieves inference latencies of approximately $34\mu$s. We validate the generated design through software reference comparisons, HLS C simulation, HLS synthesis, export, and Vivado synthesis reports. This work opens up the hls4ml toolkit to neuromorphic computing, allowing streamlined optimisation, synthesis, and deployment of SNN models for real-time inference.
Neural and Evolutionary Computing (cs.NE); Machine Learning (cs.LG)
arXiv:2606.10008 [cs.NE]
(or arXiv:2606.10008v1 [cs.NE] for this version)
https://doi.org/10.48550/arXiv.2606.10008 Focus to learn more arXiv-issued DOI via DataCite
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