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ScaleMPA addresses the critical bottleneck in real-time motion planning by shifting from tree-centric structures to a grid-native representation, thereby exposing fine-grained parallelism for high-dimensional environments. Implemented in 28 nm CMOS, this hardware accelerator achieves significant latency reductions and substantial speedups over existing state-of-the-art systems, marking a notable advancement in robotic autonomy infrastructure.
ScaleMPA: Rethinking Scalable RRT* Acceleration With a Grid-Native Representation
arXiv:2609.24497v1 Announce Type: new Abstract: Real-time motion planning remains challenging in large and high-dimensional environments. Prior acceleration of RRT* follows tree-centric state organization, which reduces per-query cost but preserves superlinear end-to-end complexity and limits parallelism through structural dependencies. This paper presents ScaleMPA, a motion-planning accelerator that rethinks RRT* with a grid-native representation. By replacing hierarchical traversal with direct grid-based access, ScaleMPA reduces the planner critical path and exposes fine-grained parallelism. To make this reformulation practical under sparse high-dimensional planning, ScaleMPA further proposes a multi-resolution grid search engine and a hash-grid memory system. Implemented in 28 nm CMOS, ScaleMPA achieves millisecond-level planning latency and delivers 4.7$\times$--44.4$\times$ speedup over state-of-the-art motion-planning accelerators.
Abstract:Real-time motion planning remains challenging in large and high-dimensional environments. Prior acceleration of RRT* follows tree-centric state organization, which reduces per-query cost but preserves superlinear end-to-end complexity and limits parallelism through structural dependencies. This paper presents ScaleMPA, a motion-planning accelerator that rethinks RRT* with a grid-native representation. By replacing hierarchical traversal with direct grid-based access, ScaleMPA reduces the planner critical path and exposes fine-grained parallelism. To make this reformulation practical under sparse high-dimensional planning, ScaleMPA further proposes a multi-resolution grid search engine and a hash-grid memory system. Implemented in 28 nm CMOS, ScaleMPA achieves millisecond-level planning latency and delivers 4.7$\times$--44.4$\times$ speedup over state-of-the-art motion-planning accelerators.
Robotics (cs.RO); Hardware Architecture (cs.AR)
arXiv:2609.24497 [cs.RO]
(or arXiv:2609.24497v1 [cs.RO] for this version)
https://doi.org/10.48550/arXiv.2609.24497 Focus to learn more arXiv-issued DOI via DataCite (pending registration)
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