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This paper introduces RTL-Sequencer, which applies modern linear sequence models—such as those used in large language models—to solve the register-transfer level (RTL) timing prediction problem. By converting logic cones into sequences and employing techniques like bidirectional modeling and differentiable training, it overcomes limitations of traditional graph-based methods regarding receptive fields and signal directionality. The approach represents a significant methodological shift where AI/ML architectures are directly leveraged to optimize hardware design automation workflows.
RTL-Sequencer: Towards Scalable RTL Timing Prediction with the Sequence-based Paradigm
arXiv:2607.15830v1 Announce Type: cross Abstract: Accurate timing prediction at the register-transfer level (RTL) is a longstanding challenge in design automation. Existing graph-based methods struggle with limited receptive fields, high complexity, and a lack of signal directionality. We present RTL-Sequencer, a novel sequence-based paradigm that enables scalable RTL timing prediction via linearizing logic cones by breadth-first traversal and applying modern linear sequence models. Furthermore, sequence models are customized by four synergistic techniques, including sequence shuffling, bidirectional modeling, differentiable modeling, and a hybrid graph-sequence architecture. Extensive experiments demonstrate significant improvements of RTL-Sequencer over state-of-the-art baselines, advancing early-stage timing optimization.
Abstract:Accurate timing prediction at the register-transfer level (RTL) is a longstanding challenge in design automation. Existing graph-based methods struggle with limited receptive fields, high complexity, and a lack of signal directionality. We present RTL-Sequencer, a novel sequence-based paradigm that enables scalable RTL timing prediction via linearizing logic cones by breadth-first traversal and applying modern linear sequence models. Furthermore, sequence models are customized by four synergistic techniques, including sequence shuffling, bidirectional modeling, differentiable modeling, and a hybrid graph-sequence architecture. Extensive experiments demonstrate significant improvements of RTL-Sequencer over state-of-the-art baselines, advancing early-stage timing optimization.
Hardware Architecture (cs.AR); Artificial Intelligence (cs.AI); Machine Learning (cs.LG)
arXiv:2607.15830 [cs.AR]
(or arXiv:2607.15830v1 [cs.AR] for this version)
https://doi.org/10.48550/arXiv.2607.15830 Focus to learn more arXiv-issued DOI via DataCite (pending registration)
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