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This paper addresses the critical challenge of deploying quantized transformer models for jet tagging on AMD Versal AI Engines within low-latency CERN LHC trigger systems. The authors introduce a reusable software framework that automatically maps dense and multi-head attention layers onto AIE tiles, generating Vitis graph code from high-level Python descriptions to enable efficient inference in resource-constrained environments.
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Reconfigurable Computing Challenge: Transformer for Jet Tagging on Versal AI Engines

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arXiv:2606.17500v1 Announce Type: new Abstract: Transformer-based models achieve strong performance for jet tagging at the CERN LHC, but deploying them in low-latency, resource-constrained trigger systems is challenging. We present an initial implementation of a quantized, integer-only transformer for jet tagging on the AMD Versal AI Engine (AIE), mapping dense and multi-head attention (MHA) layers to AIE tiles. The main contribution is a reusable software framework that represents transformer layers as composable AIE building blocks and automatically generates the corresponding Vitis graph code from a high-level Python model description. This framework provides a foundation for future research and is released as open-source software at https://github.com/KastnerRG/particle_transformer_aie.

Abstract:Transformer-based models achieve strong performance for jet tagging at the CERN LHC, but deploying them in low-latency, resource-constrained trigger systems is challenging. We present an initial implementation of a quantized, integer-only transformer for jet tagging on the AMD Versal AI Engine (AIE), mapping dense and multi-head attention (MHA) layers to AIE tiles. The main contribution is a reusable software framework that represents transformer layers as composable AIE building blocks and automatically generates the corresponding Vitis graph code from a high-level Python model description. This framework provides a foundation for future research and is released as open-source software at this https URL.

4 pages, 4 figures. In FCCM 2026 proceedings

Machine Learning (cs.LG); Hardware Architecture (cs.AR)

arXiv:2606.17500 [cs.LG]

(or arXiv:2606.17500v1 [cs.LG] for this version)

https://doi.org/10.48550/arXiv.2606.17500 Focus to learn more arXiv-issued DOI via DataCite (pending registration)

2026 IEEE 34th Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), Atlanta, GA, USA, 2026, pp. 307-310

https://doi.org/10.1109/FCCM68464.2026.00078 Focus to learn more DOI(s) linking to related resources

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