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This paper addresses the critical bottleneck in deploying deep learning models on edge devices by advocating for hardware-aware design over generic approaches. It explores specific optimization techniques like model compression and neural architecture search to reconcile algorithmic complexity with heterogeneous device constraints. For practitioners focusing on efficient AI inference, this work highlights the necessity of co-designing algorithms with underlying hardware architectures.
On Hardware-Aware Design and Optimization of Edge Intelligence
arXiv:2607.16297v1 Announce Type: cross Abstract: Edge intelligence systems, the intersection of edge computing and artificial intelligence (AI), are pushing the frontier of AI applications. However, the complexity of deep learning models and heterogeneity of edge devices make the design of edge intelligence systems a challenging task. Hardware-agnostic methods face some limitations when implementing edge systems. Thus, hardware-aware methods are attracting more attention recently. In this paper, we present our recent endeavors in hardware-aware design and optimization for edge intelligence. We delve into techniques such as model compression and neural architecture search to achieve efficient and effective system designs. We also discuss some challenges in hardware-aware paradigm.
Abstract:Edge intelligence systems, the intersection of edge computing and artificial intelligence (AI), are pushing the frontier of AI applications. However, the complexity of deep learning models and heterogeneity of edge devices make the design of edge intelligence systems a challenging task. Hardware-agnostic methods face some limitations when implementing edge systems. Thus, hardware-aware methods are attracting more attention recently. In this paper, we present our recent endeavors in hardware-aware design and optimization for edge intelligence. We delve into techniques such as model compression and neural architecture search to achieve efficient and effective system designs. We also discuss some challenges in hardware-aware paradigm.
Author's accepted version. Published in IEEE Design & Test
Hardware Architecture (cs.AR); Machine Learning (cs.LG)
arXiv:2607.16297 [cs.AR]
(or arXiv:2607.16297v1 [cs.AR] for this version)
https://doi.org/10.48550/arXiv.2607.16297 Focus to learn more arXiv-issued DOI via DataCite
IEEE Design & Test, vol. 40, no. 6, pp. 149-162, December 2023
https://doi.org/10.1109/MDAT.2023.3307558 Focus to learn more DOI(s) linking to related resources
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