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Microsoft's Maia 300 represents a significant architectural shift toward multichiplet designs for AI inference, leveraging TSMC's 2nm process to optimize data flow and reduce power consumption per token. By integrating internal SRAM caches and compressing data formats like MXFP4, the chip aims to overcome the bandwidth limitations typically associated with high-capacity HBM memory stacks. This development highlights a strategic move away from reliance on general-purpose GPUs toward specialized silicon architectures designed specifically for the efficiency demands of large-scale model inference.

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Microsoft debuts multichiplet Maia 300 inference accelerator

SiliconANGLE12 octombrie 20264 min de cititArticolul și perspectiva sunt în engleză.

Microsoft Corp. today pulled back the curtains on Maia 300, its newest internally developed artificial intelligence accelerator. The chip is optimized for inference, the process of generating responses to AI queries. Microsoft estimates that it can process 40% more tokens per megawatt than “leading GPU-based systems,” which is likely a reference to Nvidia Corp. products. […] The post Microsoft debuts multichiplet Maia 300 inference accelerator appeared first on SiliconANGLE.

Microsoft Corp. today pulled back the curtains on Maia 300, its newest internally developed artificial intelligence accelerator. The chip is optimized for inference. Microsoft estimates that it can process 40% more tokens per megawatt than “leading GPU-based systems,” which is likely a reference to Nvidia Corp. products. The company stated the Maia chip series will become its primary source of inference capacity over time. Maia 300 features four computing chiplets made using Taiwan Semiconductor Manufacturing…

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