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Illinois researchers have demonstrated a scalable monolithic 3D integration process using standard silicon that achieves a 6x density increase with 98-100% device yields. This breakthrough directly addresses the physical limits of shrinking transistors on flat chips, offering a viable industrial path to extend Moore's Law through vertical integration. The technology promises to significantly boost computing density and speed while reducing energy consumption, marking a critical step toward overcoming atomic-scale constraints in modern processors.
Illinois Engineers Stack Silicon Circuits for 6x Density Gain
Illinois engineers, led by Qing Cao, have demonstrated a scalable method for sequentially stacking silicon circuits.
Researchers led by Qing Cao of Illinois Grainger Engineering have achieved an advance in chip design, demonstrating a scalable method for directly stacking high-performance silicon circuits. This breakthrough addresses a fundamental limitation in modern computing: the physical constraints of shrinking transistors on traditional, flat chips. The team’s process allows for the creation of three-dimensional chips, potentially extending Moore’s law by increasing density and speed while reducing energy consumption. “Today it takes six microelectronic devices called transistors on a single plane to store one bit of information,” explains Associate Professor Qing Cao, Department of Materials Science and Engineering; “With vertical integration, you can distribute them across multiple layers.” This newly invented process, detailed in Nature, utilizes standard single-crystalline silicon and achieved device yields of…
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