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This study demonstrates significant progress in silicon-based quantum computing by adapting 300mm CMOS fabrication processes to reduce device variability and improve electrostatic properties. The research highlights a high yield of reproducible quantum dots with precise control over the first-electron position, marking a critical step toward scalable, industry-compatible qubit arrays. These findings validate QSOI(R) technology as a robust platform for integrating quantum devices within existing semiconductor manufacturing ecosystems.
Highly uniform first-electron position in qubit arrays fabricated on dedicated QSOI(R) 300mm commercial platform
arXiv:2609.20043v1 Announce Type: cross Abstract: We report progress toward the development of a quantum silicon-on-insulator (QSOI(R)) technology compatible with 300mm CMOS fabrication and adapted from the 28nm Fully-Depleted SOI (28nm FD-SOI) platform for scalable quantum computing. We compare quantum devices fabricated with standard 28nm FD-SOI and QSOI(R) technologies, and show striking improvements of room temperature electrostatic properties of the individual device. Moreover, the QSOI(R) technology has significantly reduced the device variability and the dispersion of device properties at the wafer level. Transistor metrics are reproduced by TCAD simulations showing that the electrostatics of the devices behave as expected for QSOI(R) technology. Wafer-scale measurements at sub-2K show reproducible quantum dots down to the few-electron regime with 69\% yield for successful charge detection of the first electron and a dispersion of the first electron position of $\mathrm{\pm 35 mV}$ over 377 quantum dots. These results establish QSOI(R) as a promising platform for CMOS-compatible quantum device co-integration.
Authors:Johan Pelloux-Prayer, Elise Prin, Giselle A. Elbaz, Pierre-Louis Julliard, Amaryllis Comiti, Clément Nguyen, Sylvain Martin, Patrick Torresani, Renan Lethiecq, Carlos Augusto Suarez Segovia, Franck Arnaud, Etienne Nowak, Tristan Meunier, Bruna Cardoso Paz
Abstract:We report progress toward the development of a quantum silicon-on-insulator (QSOI(R)) technology compatible with 300mm CMOS fabrication and adapted from the 28nm Fully-Depleted SOI (28nm FD-SOI) platform for scalable quantum computing. We compare quantum devices fabricated with standard 28nm FD-SOI and QSOI(R) technologies, and show striking improvements of room temperature electrostatic properties of the individual device. Moreover, the QSOI(R) technology has significantly reduced the device variability and the dispersion of device properties at the wafer level. Transistor metrics are reproduced by TCAD simulations showing that the electrostatics of the devices behave as expected for QSOI(R) technology. Wafer-scale measurements at sub-2K show reproducible quantum dots down to the few-electron regime with 69\% yield for successful charge detection of the first electron and a dispersion of the first electron position of $\mathrm{\pm 35 mV}$ over 377 quantum dots. These results establish QSOI(R) as a promising platform for CMOS-compatible quantum device co-integration.
Mesoscale and Nanoscale Physics (cond-mat.mes-hall); Quantum Physics (quant-ph)
arXiv:2609.20043 [cond-mat.mes-hall]
(or arXiv:2609.20043v1 [cond-mat.mes-hall] for this version)
https://doi.org/10.48550/arXiv.2609.20043 arXiv-issued DOI via DataCite (pending registration)
From: Giselle A. Elbaz [view email] [v1] Thu, 17 Sep 2026 10:51:04 UTC (2,771 KB)
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