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This research demonstrates how leveraging RISC-V's native float16 extensions enables efficient on-device training for embedded AI systems without significant performance loss or hardware overhead. By reducing memory footprints by roughly 50% compared to standard precision, the work addresses critical constraints in deploying machine learning models directly on resource-limited edge devices. The proposed framework extends existing open-source tools like AIfES with specific optimizations for transfer learning and fine-tuning scenarios.
Hardware-Software Co-Design for Float16 On-Device Training on RISC-V Single-Core
arXiv:2607.21130v1 Announce Type: cross Abstract: By leveraging standard RISC-V extensions, namely Zfh (scalar float16) and Zvfh (vector float16), this work proposes an open-source framework to enable complete on-device training on resource-constrained RISC-V single-core. Our approach allows memory footprint reduction by about 50% as compared to using float32 and with minimal model performance degradation. We also facilitate transfer learning and fine-tuning scenarios by incorporating layer-freezing capabilities. Our work builds onto AIfES, an open-source, modular and generic DNN training and inference framework for embedded systems that can be extended with custom hardware-specific functions. The benefits of float16 is further emphasized by outlining the low area overhead of Zfh on a RV64GC super-scalar out-of-order FPGA softcore (+1.15% LUT6 and +0.05% FF at 175MHz). Finally, we discuss the architecture of a Zvfh implementation within the same RISC-V core.
Abstract:By leveraging standard RISC-V extensions, namely Zfh (scalar float16) and Zvfh (vector float16), this work proposes an open-source framework to enable complete on-device training on resource-constrained RISC-V single-core. Our approach allows memory footprint reduction by about 50% as compared to using float32 and with minimal model performance degradation. We also facilitate transfer learning and fine-tuning scenarios by incorporating layer-freezing capabilities. Our work builds onto AIfES, an open-source, modular and generic DNN training and inference framework for embedded systems that can be extended with custom hardware-specific functions. The benefits of float16 is further emphasized by outlining the low area overhead of Zfh on a RV64GC super-scalar out-of-order FPGA softcore (+1.15% LUT6 and +0.05% FF at 175MHz). Finally, we discuss the architecture of a Zvfh implementation within the same RISC-V core.
Hardware Architecture (cs.AR); Artificial Intelligence (cs.AI)
arXiv:2607.21130 [cs.AR]
(or arXiv:2607.21130v1 [cs.AR] for this version)
https://doi.org/10.48550/arXiv.2607.21130 Focus to learn more arXiv-issued DOI via DataCite (pending registration)
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