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This research introduces DiffLUT-Net, a novel approach to training FPGA-native neural networks from scratch using differentiable lookup tables and learnable connectivity. By jointly optimizing truth-table entries and hardware source selection, the method achieves efficient inference with favorable accuracy-resource trade-offs without relying on standard multiply-accumulate accelerators. The work represents a significant step toward compact, hardware-aware AI models that are directly synthesizable for deployment on FPGAs.
DiffLUT-Net: Differentiable Training of FPGA LUT Networks with Learnable Connectivity
arXiv:2609.09254v1 Announce Type: cross Abstract: Field-programmable gate arrays (FPGAs) enable efficient neural-network inference, but most deployment flows either accelerate multiply-accumulate operations or convert pretrained quantized models into lookup tables (LUTs). We present DiffLUT-Net, an FPGA-native network connected by six-input LUTs that are trained from scratch. We jointly learn the 64 truth-table entries of a LUT and the source to each of its six input ports using a differentiable LUT function relaxation and hardware source selection. After training, the truth tables and connections are discretized, unused logic can be pruned, and the network is exported directly as synthesizable Verilog. Across five benchmarks, DiffLUT-Net achieves favorable accuracy-resource trade-offs. These results demonstrate the effectiveness of jointly learning LUT functions and sparse connectivity for compact FPGA-native inference. The code is available at https://github.com/TUDa-HWAI/DiffLUT-Network.
Abstract:Field-programmable gate arrays (FPGAs) enable efficient neural-network inference, but most deployment flows either accelerate multiply-accumulate operations or convert pretrained quantized models into lookup tables (LUTs). We present DiffLUT-Net, an FPGA-native network connected by six-input LUTs that are trained from scratch. We jointly learn the 64 truth-table entries of a LUT and the source to each of its six input ports using a differentiable LUT function relaxation and hardware source selection. After training, the truth tables and connections are discretized, unused logic can be pruned, and the network is exported directly as synthesizable Verilog. Across five benchmarks, DiffLUT-Net achieves favorable accuracy-resource trade-offs. These results demonstrate the effectiveness of jointly learning LUT functions and sparse connectivity for compact FPGA-native inference. The code is available at this https URL.
Machine Learning (cs.LG); Artificial Intelligence (cs.AI); Hardware Architecture (cs.AR)
arXiv:2609.09254 [cs.LG]
(or arXiv:2609.09254v1 [cs.LG] for this version)
https://doi.org/10.48550/arXiv.2609.09254 Focus to learn more arXiv-issued DOI via DataCite
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