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This research establishes a new benchmark in quantum hardware by achieving record fidelity and qubit counts (N=50) on the IBM Heron r3 chip using native CZ-based instruction sets for the Quantum Fourier Transform. The study demonstrates that Parity Architecture yields super-exponential speedups over previous swap-based methods, with potential further gains from incorporating iSWAP gates into the processor's gate set.
Demonstrating Record Fidelity for the Quantum Fourier Transform
arXiv:2604.12465v2 Announce Type: replace Abstract: We demonstrate the Parity Architecture on quantum hardware, using the quantum Fourier transform (QFT) as a benchmark. As a result, a record performance in both fidelity and qubit count is achieved using quantum processors with a native CZ-based instruction set. On the IBM Heron r3 chip, a process fidelity of the QFT algorithm of ${F \approx 10^{-2}}$ for ${N=50}$ qubits is achieved. The scaling of the speedup compared to previous swap-based methods is super-exponential $\mathcal{O}(\exp(N^2))$. Furthermore, we show that the scaling can be improved further by including iSWAP gates in the instruction set.
Abstract:We demonstrate the Parity Architecture on quantum hardware, using the quantum Fourier transform (QFT) as a benchmark. As a result, a record performance in both fidelity and qubit count is achieved using quantum processors with a native CZ-based instruction set. On the IBM Heron r3 chip, a process fidelity of the QFT algorithm of ${F \approx 10^{-2}}$ for ${N=50}$ qubits is achieved. The scaling of the speedup compared to previous swap-based methods is super-exponential $\mathcal{O}(\exp(N^2))$. Furthermore, we show that the scaling can be improved further by including iSWAP gates in the instruction set.
arXiv:2604.12465 [quant-ph]
(or arXiv:2604.12465v2 [quant-ph] for this version)
https://doi.org/10.48550/arXiv.2604.12465 Focus to learn more arXiv-issued DOI via DataCite
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