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This article focuses on Arteris expanding its portfolio to support multi-die chiplet architectures specifically for AI and high-performance computing workloads. By enabling transparent data movement across physical die boundaries, the technology addresses critical scaling challenges as monolithic SoCs reach their size limits. The development is significant because it preserves architectural intelligence and efficiency in next-generation AI systems that rely on distributed silicon rather than single chips.
Arteris Accelerates Industry Transition to Multi-Die Chiplet-Based Architecture
CAMPBELL, Calif., Sept. 16, 2026 — Arteris, Inc., a leading provider of semiconductor technology for accelerating innovation in the AI era, has announced an expansion of its multi-die portfolio that helps semiconductor companies transition from monolithic system-on-chip (SoC) designs to chiplet-based architectures for AI, HPC and consumer electronics applications, without having to reinvent how data […] The post Arteris Accelerates Industry Transition to Multi-Die Chiplet-Based Architecture appeared first on HPCwire.
CAMPBELL, Calif., Sept. 16, 2026 — Arteris, Inc., a leading provider of semiconductor technology for accelerating innovation in the AI era, has announced an expansion of its multi-die portfolio that helps semiconductor companies transition from monolithic system-on-chip (SoC) designs to chiplet-based architectures for AI, HPC and consumer electronics applications, without having to reinvent how data moves through the system. Semiconductor companies are increasingly adopting multi-die architectures to address the demands of AI computing. They are now building systems that extend beyond the practical size limits of a single die, optimizing individual chiplets for different process technologies and dividing a system across multiple dies. This introduces a new challenge: communication that previously occurred within one SoC must now cross physical chip boundaries, while maintaining performance,…
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