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This work tackles a packaging bottleneck for superconducting quantum processors: stacking chips with precise, uniform spacing without degrading qubit performance. The reported transmon coherence (T1 of about 159 µs) is comparable to planar devices, which suggests the approach doesn't sacrifice qubit quality for 3D integration. Readers should note that these are single-device results from one group, and scaling uniformity and yield across full processors remains the real test.
Accurate gap control of 3D-integrated superconducting quantum circuits using asymmetric indium architecture and multi-angle flip-chip bonding
arXiv:2610.21435v1 Announce Type: new Abstract: Flip-chip 3D integration is a key enabling technology for overcoming the routing and layout constraints of planar superconducting quantum processors, but it requires accurate and uniform control of the inter-chip spacing while preserving qubit coherence. In conventional processes, thick indium bumps are deposited symmetrically on both chips, while dedicated spacers are introduced to limit the residual tilt. Here, we present a flip-chip bonding process based on an asymmetric indium architecture, combining $20\,\mu\mathrm{m}$ thick indium bumps on the control chip with $200\,\mathrm{nm}$ thin indium pads on the qubit chip. Using electrical and microwave measurements, we demonstrate low resistance and low loss indium interconnects, and show that transmon qubits integrated with this process reach relaxation and coherence times of $T_1=(159\pm14)\,\mu\mathrm{s}$ and $T_{\mathrm{2,echo}}=(294\pm42)\,\mu\mathrm{s}$, respectively, comparable to planar devices. Combined with a multi angle compression procedure that suppresses systematic tilt, this approach reduces the average post bonding tilt to $(20\pm12)\,\mu\mathrm{rad}$. These results establish an asymmetric indium architecture combined with multi angle compression as a robust, coherence preserving route toward 3D integrated superconducting quantum processors.
Abstract:Flip-chip 3D integration is a key enabling technology for overcoming the routing and layout constraints of planar superconducting quantum processors, but it requires accurate and uniform control of the inter-chip spacing while preserving qubit coherence. In conventional processes, thick indium bumps are deposited symmetrically on both chips, while dedicated spacers are introduced to limit the residual tilt. Here, we present a flip-chip bonding process based on an asymmetric indium architecture, combining $20\,\mu\mathrm{m}$ thick indium bumps on the control chip with $200\,\mathrm{nm}$ thin indium pads on the qubit chip. Using electrical and microwave measurements, we demonstrate low resistance and low loss indium interconnects, and show that transmon qubits integrated with this process reach relaxation and coherence times of $T_1=(159\pm14)\,\mu\mathrm{s}$ and $T_{\mathrm{2,echo}}=(294\pm42)\,\mu\mathrm{s}$, respectively, comparable to planar devices. Combined with a multi angle compression procedure that suppresses systematic tilt, this approach reduces the average post bonding tilt to $(20\pm12)\,\mu\mathrm{rad}$. These results establish an asymmetric indium architecture combined with multi angle compression as a robust, coherence preserving route toward 3D integrated superconducting quantum processors.
arXiv:2610.21435 [quant-ph]
(or arXiv:2610.21435v1 [quant-ph] for this version)
https://doi.org/10.48550/arXiv.2610.21435 Focus to learn more arXiv-issued DOI via DataCite (pending registration)
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